Electrostatic discharge protection circuit for an integrated circuit and method of manufacturing

• US 6,177,298 B1
• Filed: 02/02/1998
• Issued: 01/23/2001
• Est. Priority Date: 09/03/1996
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Quigley, John H.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US09/017,139
• Time in Patent Office: 1,086 Days
• Field of Search: 438/135, 438/134, 438/139, 438/137, 438/548, 438/203, 257/355, 257/358
• US Class Current: 438/135
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An ESD protection circuit (11) includes a low capacitance diode (26), a voltage divider, a trigger transistor (16), and an SCR. Reducing the capacitance associated with the diode (26) makes the ESD protection circuit particularly suitable for RF applications. To form a low capacitance diode, the parasitic junction capacitance of the diode (26) is hidden in a like-doped well; for example, an N+ cathode (54) of the diode (26) may be folded or formed partially in an N-well (53). Because the N-well (53) does not form a junction with the N+ cathode, the junction capacitance associated with the portion of the N+ well lying inside the N-well is hidden or canceled by the N-well (53), thereby reducing the overall capacitance of the diode (26).

Claims

1. A method of manufacturing an electrostatic discharge (ESD) protection circuit for an integrated circuit comprising the steps of:

providing a semiconductor substrate of a first conductivity type;

doping a portion of the semiconductor substrate with a dopant of a second conductivity type to form a first doped region;

doping a portion of the semiconductor substrate and a portion of the first doped region with a dopant of the second conductivity type to form a second doped region;

doping a portion of the first doped region with a dopant of the first conductivity type to form a third doped region that is an emitter of a first transistor, the base of the first transistor formed by the first doped region and the collector formed by the substrate;

doping portions of the semiconductor substrate with a dopant of the second conductivity type to form a fourth doped region that is an emitter of a second transistor, the base of the second transistor formed by the substrate and the collector formed by the first doped region; and

doping portions of the semiconductor substrate with a dopant of the first conductivity type to form a fifth doped region for contacting an anode of the diode formed between the substrate and the second doped region.

2. The method of claim 1 further comprising the steps of:

forming a capacitor on the semiconductor substrate;

forming a resistor coupled to the capacitor on the semiconductor substrate, wherein the capacitor and resistor form a voltage divider network; and

forming a third transistor having a control electrode coupled to a common connection of the resistor and capacitor, a first electrode coupled to the base of the first transistor, and a second electrode coupled to the base of the second transistor.

3. The method of claim 2 further comprising the step of forming the capacitor integral with the control electrode of the third transistor.

4. A method of configuring an electrostatic discharge (ESD) protection circuit for an integrated circuit comprising the steps of:

connecting first and second transistors as a silicon controlled rectifier (SCR) where an emitter and base of the first transistor are coupled to a collector of the second transistor and an emitter and base of the second transistor are coupled to a collector of the first transistor;

providing a serial connection of a capacitor and a resistor between the emitters of the first and second transistors; and

connecting a control terminal of a third transistor to a common connection of the resistor and the capacitor and current conduction terminals to the bases of the first and second transistors.

5. The method of claim 4, further including the step of coupling a diode between the emitter of the first transistor and the emitter of the second transistor.