Method of forming dual damascene interconnects using glue material as plug material

• US 6,177,342 B1
• Filed: 05/08/1998
• Issued: 01/23/2001
• Est. Priority Date: 03/17/1998
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Tzung-Han, Chao, Li-Chieh
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): NGUYEN, HA T
• Application Number:
  US09/075,422
• Time in Patent Office: 991 Days
• Field of Search: 438/638, 438/644, 438/648, 438/643, 438/637, 438/640, 438/625, 438/628, 438/631, 438/633, 438/639, 438/653, 438/687, 438/688, 438/654, 438/685, 257/774, 257/775
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

An multi-level interconnection uses a glue layer material as a via plug or contact plug. An method of forming the multi-level interconnection includes: forming a first opening and a wider second opening in a dielectric layer, whereas the first opening exposes the conductive layer and the second opening is above the first opening; and filling the first opening with titanium, titanium nitride or tungsten nitride.

Claims

1. A method of fabricating a multi-level interconnection of a semiconductor device, wherein the multi-level interconnection is formed on a substrate, comprising:

forming a dielectric layer on a conductive layer, wherein, in the dielectric layer, there are a first opening exposing the conductive layer and a second opening above the first opening, and wherein the second opening is wider than the first opening;

forming only one homogeneous layer as a first conductive material to completely fill the first opening and partially fill the second opening, wherein the glue layer contacting said conductive layer and said dielectric layer; and

forming a second conductive material to fill the second opening.

2. A method of claim 1, wherein the conductive layer comprises one of source/drain regions.

3. A method of claim 1, wherein the conductive layer comprises a metal layer of the multi-level interconnection.

4. A method of claim 1, wherein the first conductive material has a thickness substantially larger than a radius of the first opening.

5. A method of claim 1, wherein the first conductive material comprises titanium.

6. A method of claim 1, wherein the first conductive material comprises titanium nitride.

7. A method of claim 1, wherein the first conductive material comprises tungsten nitride.

8. A method of claim 1, wherein the second conductive material comprises aluminum.

9. A method of claim 1, wherein the second conductive material comprises copper.

10. A method of claim 1, wherein the second conductive material comprises tungsten.

11. A method of fabricating a multi-level interconnection of a semiconductor device, wherein the multi-level interconnection is formed on a first conductive layer on a substrate, comprising:

forming a dielectric layer on the first conductive layer, wherein, in the dielectric layer, there are a first opening exposing the first conductive layer and a second opening above the first opening, and wherein the second opening is wider than the first opening;

forming a homogeneous second conductive layer to fill the first opening, wherein the second conductive layer has a thickness substantially larger than a depth of the first opening;

forming a third conductive layer over the substrate to fill the second opening, wherein the second conductive layer contacting said first conductive layer and said dielectric layer; and

performing an etching back process, using the dielectric layer as an etching stop layer, to remove additional third conductive layer and second conductive layer.

12. A method of claim 11, wherein the first conductive layer comprises one of source/drain regions.

13. A method of claim 11, wherein the first conductive layer comprises a metal layer of the multi-level interconnection.

14. A method of claim 11, wherein the second conductive layer is a glue layer.

15. A method of claim 11, wherein the second conductive material is a glue layer material.

16. A method of claim 11, wherein the second conductive material comprises titanium.

17. A method of claim 11, wherein the second conductive material comprises titanium nitride.

18. A method of claim 11, wherein the second conductive material comprises tungsten nitride.

19. A method of claim 11, wherein the third conductive material comprises aluminum.

20. A method of claim 11, wherein the third conductive material comprises copper.

21. A method of claim 11, wherein the third conductive material comprises tungsten.