Compensated-current mirror off-chip driver

• US 6,177,817 B1
• Filed: 04/01/1999
• Issued: 01/23/2001
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Houghton, Russell J., Wilson, Adam B., Fifield, John A.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/283,960
• Time in Patent Office: 663 Days
• Field of Search: 327/379, 327/380, 327/530, 327/538, 327/540, 327/537, 327/541, 327/108, 327/111, 327/362, 327/381
• US Class Current: 327/108
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

An off-chip driver circuit with compensated current source including a reference current amplifier and an output driver with a pull-up section. The reference current amplifier includes an input voltage Vcmn from an on chip current reference source. A reference current is established in the reference current amplifier by choosing the Beta of transistor in a current path. A feature of the circuit is that an output current is produced in the output lead of the driver circuit that is proportional to the current in the reference current amplifier, but with adjustments made for the supply voltage level and effective transistor channel length, Leff. Another feature of the circuit is that a reference current-voltage is established on the output lead of the reference current amplifier that is primarily determined by a multiple of the reference current but is reduced by a function of the supply voltage. In the circuit the output current of the driver is reduced linearly and predictably with the supply voltage.

Claims

1. An off-chip driver circuit for integrated circuits comprising:

a reference current amplifier circuit connected to an input voltage (Vcmn) for providing a reference current, and a reference current-voltage (Vbias2) on an output lead of the reference current amplifier circuit,

an output driver circuit including a pull-up circuit stage having an input lead connected to the reference current amplifier circuit output lead and responsive to the reference current-voltage (Vbias2) to produce an output current on an output lead proportional to the reference current provided by the reference current amplifier, wherein the reference current amplifier includes first and second transistor devices connected in series to form a first current path and third and fourth transistor devices connected in series to form a second current path, wherein the reference current from the reference current amplifier flows in the first current path and the reference current has a level that is determined by the Beta of the second transistor of the first current path.

2. The off-chip driver circuit of claim 1 wherein the first transistor device of the first current path and the third transistor device of the second current path have effective channel lengths Leff that are dissimilar.

3. The off-chip driver circuit of claim 1 wherein the output current on the output lead of the output driver circuit is proportional to the reference current in the first current path.

4. The off-chip driver circuit of claim 1 wherein a current flows in the second current path of the reference current amplifier that is proportional to the reference current in the first current path multiplied by the Beta of the third transistor of the second current path divided by the Beta of the first transistor of the first current path.

5. The off-chip driver circuit of claim 1 further including a source of supply voltage (VCCQ) and wherein the reference current amplifier and the pull-up stage of the output driver circuit are connected to the source of supply voltage (VCCQ), and wherein the reference current-voltage (Vbias2) is a multiple of the reference current in the first current path reduced by a function of the supply voltage (VCCQ).

6. The off-chip driver circuit of claim 1 wherein the output driver circuit includes an output transistor device connected to the driver circuit output lead, a delay element for providing a delay signal, and a first and a second pull-down circuit path connected to the gate of the output transistor device to discharge the output transistor, wherein the first pull down path is connected to the delay element and conducts a transient current at the output transistor device for a transient time period and the second pull down path maintains the output current on the driver circuit output lead at a predetermined current level after the end of the transient time period.

7. The off-chip driver circuit of claim 5 further including a delay element for providing a delay signal, fifth and sixth transistor devices connected in series, the fifth transistor device having a gate connected to a data input signal, the sixth transistor device having a gate connected to the delay element and a seventh transistor device connected is series with the fifth and sixth transistor devices and having a gate connected to the output lead of the reference current amplifier circuit and responsive to the reference current-voltage (Vbias2) thereon, the fifth, sixth and seventh series connected transistor devices forming a current path for conducting a transient current having a time period determined by the delay signal from the delay element.

8. The off-chip driver circuit of claim 7 further including an eighth transistor device connected to the fifth transistor device and to the output transistor device wherein the fifth, sixth, seventh and eighth transistor devices control the current in the output transistor device to provide a compensated-current mirror output current level that is proportional to the current flowing in the fifth, sixth and seventh series connected transistor devices.

9. The off-chip driver circuit of claim 8 further including a ninth and a tenth transistor device connected in series to the gate of the fourth transistor device and the gate of the output transistor device to provide a maintenance drive current path that is established by a DC path through the ninth and tenth transistor devices for conducting a maintenance current when the transient current flowing through the fifth, sixth and seventh transistor devices ends.

10. The off-chip driver circuit of claim 1 wherein the reference current amplifier and the pull-up stage of the output driver circuit are connected to a source of supply voltage (VCCQ), and wherein the reference current-voltage (Vbias2) on the output lead from the reference current amplifier is adjusted in response to a change in the supply voltage (VCCQ) connected to the reference current amplifier.

11. The off-chip driver circuit of claim 10 wherein the reference current amplifier is connected to the source of supply voltage (VCCQ) through a resistive element and an eleventh and a twelfth transistor device connected in series to the output lead from the reference current amplifier, and wherein a current through the eleventh transistor device is increased by an increase change in the supply voltage (VCCQ).

12. The off-chip driver circuit of claim 11 wherein the increased current through the eleventh transistor device is mirrored to a thirteenth transistor device to reduce the current flowing through the fourth transistor device of the second current path to provide a linear relationship between the supply voltage (VCCQ) and the reference-current voltage (Vbias2).