Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate

• US 6,177,826 B1
• Filed: 04/02/1998
• Issued: 01/23/2001
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mashiko, Koichiro, Wada, Yoshiki, Ueda, Kimio
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US09/053,700
• Time in Patent Office: 1,027 Days
• Field of Search: 327/534, 327/434, 327/437, 327/576, 327/199, 327/214, 327/225, 326/121, 326/112, 326/119, 326/9, 326/17, 326/31, 326/33, 326/34
• US Class Current: 327/534
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

Claims

1. A Silicon-On-Insulator (SOI) CMOS circuit comprising:

first and second PMOS transistors connected in series to each other, each of said PMOS transistors having its body and gate connected to each other, and the gate of said first PMOS transistor connected to a first input terminal, and the gate of said second PMOS transistor connected to a second input terminal; and

an NMOS transistor connected to one of said PMOS transistors, said NMOS transistor having its body connected to a low reference potential having a value of ground

wherein turning said first and said second PMOS transistors from an OFF state to an ON state increases a current drive ability of each of said first and said second PMOS transistors to approach a current drive ability of said NMOS transistor.

2. The SOI CMOS circuit according to claim 1, further comprising first and second potential limiting circuits connected between the body and gate of said first and second PMOS transistors, respectively, for setting a lower limit of the potential of the body of each of said PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

3. The SOI CMOS circuit according to claim 2, wherein each of said first and second potential limiting circuits includes a third PMOS transistor having its source connected to the gate of a corresponding one of said first and second PMOS transistors, and its gate connected to its drain and the body of the corresponding one of said first and second PMOS transistors.

4. The SOI CMOS circuit according to claim 1, wherein the gate of said NMOS transistor is connected to said first input terminal.

5. The SOI CMOS circuit according to claim 1, further including an other NMOS transistor connected to said one of said PMOS transistors, said other NMOS transistor having its body connected to the low reference potential having the value of ground.

6. The SOI CMOS circuit according to claim 5, wherein the gate of said NMOS transistor is connected to said first input terminal, and the gate of said other NMOS transistor is connected to said second input terminal.

7. The SOI CMOS circuit according to claim 5, further comprising first and second potential limiting circuits connected between the body and gate of said first and second PMOS transistors, respectively, for setting a lower limit of the potential of the body of each of said first and second PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

8. The SOI CMOS circuit according to claim 7, wherein each of said first and second potential limiting circuits includes a third PMOS transistor having its source connected to the gate of a corresponding one of said first and second PMOS transistors, and its gate connected to its drain and the body of the corresponding one of said first and second PMOS transistors.

9. The SOI CMOS circuit according to claim 1, wherein said first and said second PMOS transistors each have a lower current drive ability than said NMOS transistor when a first potential having the value of ground is applied to the body of said NMOS transistor and a second potential having a value higher than the value of ground is applied to the bodies of said first and second PMOS transistors, the value of the second potential being equal to a value of high logic level applied to the gate of said first PMOS transistor.

10. The SOI CMOS circuit according to claim 2, wherein each of said first and second potential limiting circuits includes an MOS transistor having a drain and a gate connected to each other.

11. The SOI CMOS circuit according to claim 2, wherein each of said first and second potential limiting circuits includes an MOS transistor having a drain and a gate connected to each other.