Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate
First Claim
1. A Silicon-On-Insulator (SOI) CMOS circuit comprising:
- first and second PMOS transistors connected in series to each other, each of said PMOS transistors having its body and gate connected to each other, and the gate of said first PMOS transistor connected to a first input terminal, and the gate of said second PMOS transistor connected to a second input terminal; and
an NMOS transistor connected to one of said PMOS transistors, said NMOS transistor having its body connected to a low reference potential having a value of ground wherein turning said first and said second PMOS transistors from an OFF state to an ON state increases a current drive ability of each of said first and said second PMOS transistors to approach a current drive ability of said NMOS transistor.
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Accused Products
Abstract
A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.
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Citations
11 Claims
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1. A Silicon-On-Insulator (SOI) CMOS circuit comprising:
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first and second PMOS transistors connected in series to each other, each of said PMOS transistors having its body and gate connected to each other, and the gate of said first PMOS transistor connected to a first input terminal, and the gate of said second PMOS transistor connected to a second input terminal; and
an NMOS transistor connected to one of said PMOS transistors, said NMOS transistor having its body connected to a low reference potential having a value of ground wherein turning said first and said second PMOS transistors from an OFF state to an ON state increases a current drive ability of each of said first and said second PMOS transistors to approach a current drive ability of said NMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification