Semiconductor integrated circuit with well potential control circuit

• US 6,177,831 B1
• Filed: 07/15/1996
• Issued: 01/23/2001
• Est. Priority Date: 04/24/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoneda, Hirokazu, Watanabe, Tetsuya
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US08/679,951
• Time in Patent Office: 1,653 Days
• Field of Search: 327/538, 327/537, 327/536, 327/535, 327/534, 327/530, 327/541, 327/543, 327/566
• US Class Current: 327/537
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

A semiconductor integrated circuit which effects the subtle control of the well or substrate potential of a circuit in accordance with the operating frequency, the signal multiplication rate from a PLL circuit, the source voltage or the operating state of the circuit, thereby adjusting the operating speed of the circuit and reducing the consumption of electricity.

Claims

1. A semiconductor integrated circuit comprising:

at least one circuit performing a given function and including at least one transistor having a well; and

a potential control circuit receiving an input signal from outside said potential control circuit and said at least one circuit, said potential control circuit varying the potential of said well of said at least one transistor to any of a multiplicity of potentials within a range of potentials between a saturation value and zero of said at least one transistor of said at least one circuit,

wherein said potential of said well is controlled to be a potential within said range of potentials corresponding to an existing value of said input signal, wherein a line representing said correspondence between said potential of said well and said existing value of said input signal is a continuous line,

wherein said input signal from outside said potential control circuit and said at least one circuit adjusts an operating speed of said at least one transistor to be one of any of a multiplicity of different speeds; and

wherein the existing value of said input signal is related to a frequency, and the potential control circuit controls the well potential in accordance with the frequency.

2. The semiconductor integrated circuit according to claim 1,

wherein the existing value of said input signal is related to a signal multiplication rate outputted from a PLL circuit, and

the potential control circuit comprises:

a first conductive MOS transistor whose gate is connected to a first source terminal, and whose source and well are connected to a second source terminal;

a primary second conductive MOS transistor whose gate is connected to a drain of the first conductive MOS transistor, whose drain is connected to the drain of the first conductive MOS transistor, for providing an N well control signal;

a secondary second conductive MOS transistor whose gate and drain are connected to a source of the primary second conductive MOS transistor;

a tertiary second conductive MOS transistor whose gate is connected to the first source terminal, and whose drain is connected to a source of the secondary second conductive MOS transistor; and

a quaternary second conductive MOS transistor whose gate is connected to an input terminal for receiving a reversing control signal, whose drain is connected to a source of the tertiary second conductive MOS transistor, and whose source is connected to a ground terminal.

3. The semiconductor integrated circuit according to claim 1, further comprising:

an identification circuit for identifying the operational or non-operational state of at least part of the semiconductor integrated circuit,

wherein the existing value of said input signal is an identification signal from the identification circuit, and

wherein the potential control circuit comprises;

a first conductive MOS transistor whose gate is connected to a first source terminal, and whose source and well are connected to a second source terminal;

a primary second conductive MOS transistor whose gate is connected to a drain of the first conductive MOS transistor, whose drain is connected to the drain of the first conductive MOS transistor, for providing an N well control signal;

a secondary second conductive MOS transistor whose gate and drain are connected to a source of the primary second conductive MOS transistor;

a tertiary second conductive MOS transistor whose gate is connected to the first source terminal, and whose drain is connected to a source of the secondary second conductive MOS transistor; and

a quaternary second conductive MOS transistor whose gate is connected to an input terminal for receiving a reversing control signal, whose drain is connected to a source of the tertiary second conductive MOS transistor, and whose source is connected to a ground terminal.

4. The semiconductor integrated circuit according to claim 1, wherein the potential control circuit comprises;

a first conductive MOS transistor whose gate is connected to a first source terminal, and whose source and well are connected to a second source terminal;

a primary second conductive MOS transistor whose gate is connected to a drain of the first conductive MOS transistor, whose drain is connected to the drain of the first conductive MOS transistor, for providing an N well control signal;

a secondary second conductive MOS transistor whose gate and drain are connected to a source of the primary second conductive MOS transistor;

a tertiary second conductive MOS transistor whose gate is connected to the first source terminal, and whose drain is connected to a source of the secondary second conductive MOS transistor; and

a quaternary second conductive MOS transistor whose gate is connected to an input terminal for receiving a reversing control signal, whose drain is connected to a source of the tertiary second conductive MOS transistor, and whose source is connected to a ground terminal.

5. The semiconductor integrated circuit according to claim 1, wherein the potential control circuit comprises;

a second conductive MOS transistor whose gate is connected to a ground terminal, and whose source and well are connected to a first negative source terminal;

a quaternary first conductive MOS transistor whose gate is connected to a drain of the second conductive MOS transistor, whose drain is connected to the drain of the second conductive MOS transistor, for providing a p well control signal;

a tertiary first conductive MOS transistor whose gate and drain are connected to a source of the quaternary first conductive MOS transistor;

a secondary first conductive MOS transistor whose gate is connected to the ground terminal, and whose drain is connected to a source of the tertiary first conductive MOS transistor; and

a primary first conductive MOS transistor whose gate is connected to an input terminal for receiving a control signal, whose drain is connected to a source of the secondary first conductive MOS transistor, and whose source is connected to a first source terminal.

6. The semiconductor integrated circuit according to claim 1,

wherein the existing value of said input signal is related to a signal multiplication rate outputted from a PLL circuit, and

the potential control circuit comprises;

a second conductive MOS transistor whose gate is connected to a ground terminal, and whose source and well are connected to a first negative source terminal;

a quaternary first conductive MOS transistor whose gate is connected to a drain of the second conductive MOS transistor, whose drain is connected to the drain of the second conductive MOS transistor, for providing a p well control signal;

a tertiary first conductive MOS transistor whose gate and drain are connected to a source of the quaternary first conductive MOS transistor;

a secondary first conductive MOS transistor whose gate is connected to the ground terminal, and whose drain is connected to a source of the tertiary first conductive MOS transistor; and

a primary first conductive MOS transistor whose gate is connected to an input terminal for receiving a control signal, whose drain is connected to a source of the secondary first conductive MOS transistor, and whose source is connected to a first source terminal.

7. The semiconductor integrated circuit according to claim 1, further comprising:

an identification circuit for identifying the operational or non-operational state of at least part of the semiconductor integrated circuit,

wherein the existing value of said input signal is an identification signal from the identification circuit, and

wherein the potential control circuit comprises;

a second conductive MOS transistor whose gate is connected to a ground terminal, and whose source and well are connected to a first negative source terminal;

a quaternary first conductive MOS transistor whose gate is connected to a drain of the second conductive MOS transistor, whose drain is connected to the drain of the second conductive MOS transistor, for providing a p well control signal;

a tertiary first conductive MOS transistor whose gate and drain are connected to a source of the quaternary first conductive MOS transistor;

a secondary first conductive MOS transistor whose gate is connected to the ground terminal, and whose drain is connected to a source of the tertiary first conductive MOS transistor; and

a primary first conductive MOS transistor whose gate is connected to an input terminal for receiving a control signal, whose drain is connected to a source of the secondary first conductive MOS transistor, and whose source is connected to a first source terminal.

8. A semiconductor integrated circuit comprising:

at least one circuit performing a given function and including at least one transistor on a substrate; and

a potential control circuit receiving an input signal from outside said potential control circuit and said at least one circuit, said potential control circuit varying the potential of said substrate of said at least one transistor to any of a multiplicity of potentials within a range of potentials between a saturation value and zero of said at least one transistor of said at least one circuit,

wherein said potential of said substrate is controlled to be a potential within said range of potentials corresponding to an existing value of said input signal, wherein a line representing said correspondence between said potential of said substrate and said existing value of said input signal is a continuous line,

wherein said input signal from outside said potential control circuit and said at least one circuit adjusts an operating speed of said at least one transistor to be one of any of a multiplicity of different speeds,

wherein the existing value of said input signal is related to a frequency, and

wherein the potential control circuit controls the substrate potential in accordance with the frequency.

9. The semiconductor integrated circuit according to claim 8,

wherein the existing value of said input signal is related to a signal multiplication rate outputted from a PLL circuit, and

wherein the potential control circuit comprises:

a first conductive MOS transistor whose gate is connected to a first source terminal, and whose source and well are connected to a second source terminal;

a primary second conductive MOS transistor whose gate is connected to a drain of the first conductive MOS transistor, whose drain is connected to the drain of the first conductive MOS transistor, for providing an N well control signal;

a secondary second conductive MOS transistor whose gate and drain are connected to a source of the primary second conductive MOS transistor;

a tertiary second conductive MOS transistor whose gate is connected to the first source terminal, and whose drain is connected to a source of the secondary second conductive MOS transistor; and

a quaternary second conductive MOS transistor whose gate is connected to an input terminal for receiving a reversing control signal, whose drain is connected to a source of the tertiary second conductive MOS transistor, and whose source is connected to a ground terminal.

10. The semiconductor integrated circuit according to claim 8, further comprising:

an identification circuit for identifying the operational or non-operational state of at least part of the semiconductor integrated circuit,

wherein the existing value of said input signal is an identification signal from the identification circuit, and

wherein the potential control circuit comprises;

a first conductive MOS transistor whose gate is connected to a first source terminal, and whose source and well are connected to a second source terminal;

a primary second conductive MOS transistor whose gate is connected to a drain of the first conductive MOS transistor, whose drain is connected to the drain of the first conductive MOS transistor, for providing an N well control signal;

a secondary second conductive MOS transistor whose gate and drain are connected to a source of the primary second conductive MOS transistor;

a tertiary second conductive MOS transistor whose gate is connected to the first source terminal, and whose drain is connected to a source of the secondary second conductive MOS transistor; and

a quaternary second conductive MOS transistor whose gate is connected to an input terminal for receiving a reversing control signal, whose drain is connected to a source of the tertiary second conductive MOS transistor, and whose source is connected to a ground terminal.

11. The semiconductor integrated circuit according to claim 8,

wherein the existing value of said input signal is related to a signal multiplication rate outputted from a PLL circuit, and

wherein the potential control circuit comprises:

a second conductive MOS transistor whose gate is connected to a ground terminal, and whose source and well are connected to a first negative source terminal;

a quaternary first conductive MOS transistor whose gate is connected to a drain of the second conductive MOS transistor, whose drain is connected to the drain of the second conductive MOS transistor, for providing a p well control signal;

a tertiary first conductive MOS transistor whose gate and drain are connected to a source of the quaternary first conductive MOS transistor;

a secondary first conductive MOS transistor whose gate is connected to the ground terminal, and whose drain is connected to a source of the tertiary first conductive MOS transistor; and

a primary first conductive MOS transistor whose gate is connected to an input terminal for receiving a control signal, whose drain is connected to a source of the secondary first conductive MOS transistor, and whose source is connected to a first source terminal.

12. The semiconductor integrated circuit according to claim 8, further comprising:

an identification circuit for identifying the operational or non-operational state of at least part of the semiconductor integrated circuit,

wherein the existing value of said input signal is an identification signal from the identification circuit, and

wherein the potential control circuit comprises;

a second conductive MOS transistor whose gate is connected to a ground terminal, and whose source and well are connected to a first negative source terminal;

a quaternary first conductive MOS transistor whose gate is connected to a drain of the second conductive MOS transistor, whose drain is connected to the drain of the second conductive MOS transistor, for providing a p well control signal;

a tertiary first conductive MOS transistor whose gate and drain are connected to a source of the quaternary first conductive MOS transistor;

a secondary first conductive MOS transistor whose gate is connected to the ground terminal, and whose drain is connected to a source of the tertiary first conductive MOS transistor; and

a primary first conductive MOS transistor whose gate is connected to an input terminal for receiving a control signal, whose drain is connected to a source of the secondary first conductive MOS transistor, and whose source is connected to a first source terminal.

13. A semiconductor integrated circuit comprising:

at least one circuit performing a given function and including at least two transistors each having a well; and

a potential control circuit receiving an input signal from outside said potential control circuit and said at least one circuit, said potential control circuit separately and independently varying the potential of said respective wells of said at least two transistors to any of a multiplicity of potentials within a range of potentials between a saturation value and zero of said at least two transistors of said at least one circuit,

wherein said potential of said wells are individually and separately controlled to be a potential within said range of potentials corresponding to an existing value of said input signal, wherein a line representing said correspondence between said potential of each of said wells and said existing value of said input signal is a continuous line, and

wherein said input signal from outside said potential control circuit and said at least one circuit adjusts an operating speed of said at least two transistors to be one of any of a multiplicity of different speeds.