Dual floating gate programmable read only memory cell structure and method for its fabrication and operation

• US 6,178,113 B1
• Filed: 08/12/1998
• Issued: 01/23/2001
• Est. Priority Date: 04/08/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Bensistant, Francis L., Gonzalez, Fernando
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/132,667
• Time in Patent Office: 895 Days
• Field of Search: 365/185.03, 365/185.1, 365/185.19, 365/185.24, 257/315, 257/316, 257/219
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation

Abstract

A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.

Claims

1. A memory cell comprising:

a word line;

first and second digit lines;

a transistor comprising a control gate region connected to said word line, active doped regions respectively connected to said first and second digit lines, and at least first and second floating gate regions located beneath said control gate region;

at least one of said floating gate regions being capacitively coupled to a respective active doped region through a dielectric region located below said at least one floating gate region and through a dielectric region located on a sidewall of said at least one floating gate region; and

an electrically conductive material extending from at least a first one of said active doped regions to a position adjacent to said at least one floating gate region such that said electrically conductive material is coupled to said dielectric region located on a sidewall of said at least one floating gate region.

2. A memory cell as in claim 1 wherein said memory cell is formed in an integrated circuit and said at least first and second floating gate regions are located adjacent each other and separated by an insulator.

3. A memory cell as in claim 1 wherein each of said floating gate regions is arranged to store respective charges enabling said memory cell to store a multi-bit digital value.

4. A memory cell as in claim 3 wherein said multi-bit digital value represents two bits of digital information.

5. A memory cell as in claim 3 wherein said multi-bit digital value represents more than two bits of digital information.

6. A memory cell as in claim 3 further comprising an electronic circuit connected to said word line and first and second digit lines for operating said transistor to write and read said multi-bit digit value to and from said memory cell.

7. A memory cell as in claim 6 wherein said transistor stores at least two separate binary digit values by the charges stored in said first and second floating gate regions.

8. A memory cell as in claim 6 wherein said electronic circuit applies a first voltage to said word line and, for at least a portion of the duration of the application of said first voltage to said word line, a second voltage to a digit line connected with one of said first and second floating gate regions to store a charge in said one floating gate region.

9. A memory cell as in claim 8 wherein said electronic circuit further applies a third voltage to a digit line associated with the other of said first and second floating gate regions for at least a portion of the duration of the application of said first voltage to store a charge in said other floating gate region.

10. A memory cell as in claim 4 wherein a gate region threshold voltage Vt of said transistor is related to the value of the charges stored in said first and second floating gate regions.

11. A memory cell as in claim 9 wherein said electronic circuit applies said second and third voltages in sequence for at least a portion of the duration that said electronic circuit applies said first voltage to said word line.

12. A memory cell as in claim 6 wherein said electronic circuit applies a fourth voltage to said word line, and for at least a portion of the duration of the application of said fourth voltage to said word line, a fifth voltage to a digit line associated with one of said first and second floating gate regions to read a bit value defining charge stored in said one floating gate region.

13. A memory cell as in claim 12 wherein said electronic circuit applies a sixth voltage to a digit line associated with the other of said first and second floating gate regions for at least a portion of the duration of the application of said fourth voltage to said word line to read a bit value defining charge stored in said other floating gate region.

14. A memory cell as in claim 13 wherein said electronic circuit applies said fifth and sixth voltages in sequence for at least a portion of the duration that said electronic circuit applies said fourth voltage to said word line.

15. A memory cell as in claim 1 wherein said memory cell is part of a flash memory array.

16. A memory cell as in claim 13 further comprising a decoder responsive to the charges read from said first and second floating gate regions for providing a multi-bit binary value representing the charges stored in said first and second floating gate regions.

17. A memory cell as shown in claim 6, wherein a gate region turn on threshold voltage Vt of said transistor is related to the value of the charges stored in said first and second floating gates and wherein said electronic circuit supplies voltage to said row and first and second digit lines in a manner which enables said threshold voltage Vt to be determined.

18. A memory cell as in claim 17, further comprising a decoder for providing a multi-bit value in response to a determined threshold voltage Vt.

19. A memory cell as in claim 17, wherein said electronic circuit supplies a ramp voltage to said word line while biasing said source and drain regions through said digit lines in a manner which causes said transistor to turn on when said ramp voltage reaches said gate region threshold voltage Vt, a representation of said ramp voltage at the time of turn on of said transistor being decoded to thereby read a multi-bit digit value from said memory cell.

20. A memory cell as in claim 1, wherein each of said floating gate regions is capacitively coupled to a respective active doped region through a dielectric region located below it and through a dielectric region located on one of its sidewalls.

21. A memory cell as in claim 1, wherein said sidewall dielectric region connects with a conductive area, said conductive area providing a conductive path connecting an active doped region associated with said at least one floating gate region with an associated digit line.

22. A memory cell as in claim 21, wherein said conductive area is a conductive plug.

23. A memory cell as in claim 21, wherein said sidewall dielectric region runs the length of said at least one floating gate region and said conductive area connects with a portion of said sidewall dielectric region.

24. A memory cell as in claim 1, wherein said sidewall dielectric region is formed of an oxide layer.

25. A memory cell as in claim 1, wherein said sidewall dielectric region is formed of an ONO layer.

50. The memory cell of claim 1, wherein said electrically conductive material comprises at least one conductive plug.

26. A memory cell comprising:

a word line;

first and second digit lines;

a transistor comprising a control gate region connected to said word line, active doped regions respectively connected to said first and second digit lines, and a floating gate region located beneath said control gate region, said floating gate region being capacitively coupled to one of said actively doped regions through a dielectric region located below said floating gate region and through a sidewall dielectric region; and

an electrically conductive material extending from said actively doped region with which the floating gate region is capacitively coupled to a position adjacent to said floating gate region such that said electrically conductive material is coupled to said sidewall dielectric region.

27. A memory cell as in claim 26, wherein said sidewall dielectric region connects with a conductive area, said conductive area providing a conductive path connecting an active doped region associated with said at least one floating gate region with an associated digit line.

28. A memory cell as in claim 27, wherein said conductive area is a conductive plug.

29. A memory cell as in claim 26, wherein said sidewall dielectric region runs the length of said at least one floating gate region and said conductive area connects with a portion of said sidewall dielectric region.

30. A memory cell as in claim 26, wherein said sidewall dielectric region is formed of an oxide layer.

31. A memory cell as in claim 26, wherein said sidewall dielectric region is formed of an ONO layer.

51. The memory cell of claim 26, wherein said electrically conductive material comprises at least one conductive plug.

32. A computer system comprising:

a processor and a flash memory connected to said processor for storing information used by said processor, said flash memory comprising a plurality of arrayed memory cells, at least some of said arrayed memory cells comprising;

a word line;

first and second digit lines;

a transistor comprising a control gate region connected to said word line, active doped regions respectively connected to said first and second digit lines, and at least first and second floating gate regions located beneath said control gate region;

at least one of said floating gate regions being capacitively coupled to a respective active doped region through a dielectric region located below said at least one floating gate region and through a dielectric region located on a sidewall of said at least one floating gate region; and

an electrically conductive material extending from said respective active doped region to a position adjacent to said at least one floating gate region such that said electrically conductive material is coupled to said dielectric region located on a sidewall of said at least one floating gate region.

33. A computer system as in claim 32, wherein said transistor is formed in an integrated circuit and said at least first and second floating gate regions are located adjacent each other separated by an insulator.

34. A computer system as in claim 32, wherein each of said floating gate regions is arranged to store a separate charge enabling said transistor to store a multi-bit digital value.

35. A computer system as in claim 34, wherein said multi-bit digital value represents two bits of digital information.

36. A computer system as in claim 34, wherein said multi-bit digital value represents more than two bits of digital information.

37. A computer system as in claim 34, further comprising an electronic circuit connected to said word line and first and second digit lines for operating said transistor to write and read said multi-bit digit value to and from said memory cell.

38. A computer system as in claim 34, wherein said electronic circuit applies a first voltage to said word line and, for at least a portion of the duration of the application of said first voltage to said word line, a second voltage to a digit line connected with one of said first and second floating gate regions to store a bit value defining charge in said one floating gate region.

39. A computer system as in claim 38, wherein said electronic circuit further applies a third voltage to a digit line associated with the other of said first and second floating gates for at least a portion of the duration of the application of said first voltage to said word line to store a bit value defining charge in said other floating gate region.

40. A computer system as in claim 34, wherein a gate region threshold voltage Vt of said transistor is related to the value of the charges stored in said first and second floating gate regions.

41. A computer system as in claim 39, wherein said electronic circuit applies said second and third voltages in sequence for at least a portion of the duration that said first electronic circuit applies said first voltage to said word line.

42. A computer system as in claim 34, wherein said electronic circuit applies a fourth voltage to said word line and for at least a portion of the duration of the application of said fourth voltage to said word line, a fifth voltage to a digit line associated with one of said first and second floating gate regions to read a bit value defining charge stored in said one floating gate region.

43. A computer system as in claim 42, wherein said electronic circuit applies a sixth voltage to a digit line associated with the other of said first and second floating gate regions for at least a portion of the duration of the application of said fourth voltage to said word line to read a bit value defining charge stored in said other floating gate.

44. A computer system as in claim 34, wherein said electronic circuit applies said fifth and sixth voltages for at least a portion of the duration that said electronic circuit applies said fourth voltage to said word line.

45. A computer system as in claim 32, wherein said memory cell is part of a flash memory array.

46. A computer system as in claim 43, further comprising a decoder responsive to the charges read from said first and second floating gate regions for providing a multi-bit binary value representing the charges stored in said first and second floating gate regions.

47. A computer system as in claim 37, wherein a gate region turn on threshold voltage Vt of said transistor is related to the value of the charges stored in said first and second floating gates and wherein said electronic circuit supplies voltage to said row and first and second digit lines in a manner which enables said threshold voltage Vt to be determined.

48. A computer system as in claim 47, further comprising a decoder for providing a multi-bit value in response to a determined threshold voltage Vt.

49. A computer system as in claim 47, wherein said electronic circuit supplies a ramp voltage to said word line while biasing said source and drain regions through said digit lines in a manner which causes said transistor to turn on when said ramp voltage reaches said gate threshold voltage Vt, a representation of said ramp voltage at the time of turn on of said transistors being decoded to thereby read a multi-bit digit value from said memory cell.

52. The system of claim 32, wherein said electrically conductive material comprises at least one conductive plug.