System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same.

• US 6,178,466 B1
• Filed: 06/12/1998
• Issued: 01/23/2001
• Est. Priority Date: 06/12/1998
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Gilbertson, Roger Lee, Bauman, Mitchell Anthony
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/096,822
• Time in Patent Office: 956 Days
• Field of Search: 710/3, 710/107, 710/126, 709/207
• US Class Current: 710/3
• CPC Class Codes: G06F 13/1657 Access to multiple memories

Abstract

A control system and interface is provided for controlling the transmission of address and data signals via independently operative bi-directional address and data interfaces, respectively, within a data processing system. The system allows address signals to be transferred via the address interface either before, or after, associated data signals are transferred. The address interface operates at a rate which is independent of the rate achieved on the data interface. Address signals transferred on the address interface are stored in one of a plurality of address storage devices depending on request type. A routing circuit associates later-provided data signals with the address storage device storing the associated address signals, and a correlation circuit allows the address storage device to record the data transfer with the associated address signals. According to one embodiment, the correlation is performed using a pointer indicative of a storage location temporarily storing the data signals. If the data signals are transferred prior to the associated address signals, the data signals are temporarily stored until the associated address signals are transferred, sorted, and associated with a selected one of the address storage devices. Following correlation of address and data signals, the associated request is eligible for processing based on the availability of the requested resource.

Claims

1. For use in a data processing system having a first unit and a second unit, wherein the first unit is capable of making requests to the second unit and each of the requests includes address signals and predetermined ones of the requests including data signals, an interface system for coupling the first unit to the second unit to transfer the requests from the first unit to the second unit, comprising:

an address interface directly coupling the first unit to the second unit to perform selected address transfer operations, each of said address transfer operations to transfer address signals associated with a respective one of the requests;

a plurality of address storage devices coupled to said address interface, each one of said plurality of address storage devices arranged to store address signals in any order within said plurality of address storage devices, said address signals being associated with predetermined ones of said address transfer operations;

a data interface directly coupling the first unit to the second unit to perform selected data transfer operations independently of said address transfer operations performed by said address interface, each of said data transfer operations to transfer data signals and each of said data transfer operations being associated with a respective one of said address transfer operations; and

a data routing logic circuit coupled to said data interface, coupled to said address interface, and coupled to each of said plurality of address storage devices, said data routing logic circuit to detect each occurrence of said data transfer operations and to associate said each occurrence of said data transfer operations to the one of said plurality of address storage devices coupled to store address signals for said respective one of said address transfer operations.

2. The interface system of claim 1, wherein each of said plurality of address storage devices further includes a correlation circuit to correlate the data signals for any one of said associated data transfer operations with stored ones of the address signals for said respective one of said address transfer operations.

3. The interface system of claim 2, and further including a plurality of priority logic circuits, each coupled to a different associated one of the plurality of address storage devices, each to detect when one of said data transfer operations and said respective one of said address transfer operations has been correlated by said correlation circuit, and to thereafter schedule said associated request for processing according to a predetermined priority scheme.

4. The interface system of claim 1, wherein each of said address storage devices include circuits for allowing the storage of address signals transferred during a predetermined maximum number of address transfer operations, and wherein each of said predetermined maximum number of address transfer operations may be associated with a data transfer operation which has not yet been performed.

5. The interface system of claim 1, wherein each of said address transfer operations are indicative of a request type, and wherein each of said address storage devices further includes circuits to store said predetermined different ones of the address transfer operations based on said indicated request type.

6. The interface system of claim 1, wherein said data routing logic circuit further includes data-before-address circuits to temporarily store data signals associated with a data transfer operation which is performed prior to said respective one of said address transfer operations until said respective one of said address transfer operations is performed.

7. The interface system of claim 1, wherein said address interface is bi-directional and includes address circuits to allow the second unit to transfer address signals to the first unit substantially simultaneously with said first unit performing one of said data transfer operations on said data interface.

8. The interface system of claim 1, wherein said data interface is bi-directional and includes data circuits to allow the second unit to transfer data signals to the first unit substantially simultaneously with said first unit performing one of said address transfer operations on said data interface.

9. The interface system of claim 1, and further including control circuits coupled to said address interface to allow said address interface to perform a number of said address transfer operations in a given period of time, said number of said address transfer operations being unrelated to the number of said data transfer operations performed by said data interface in said period of time.

10. In a system having a first unit and a second unit, the first unit being coupled directly to the second unit via an address interface and a data interface, the address interface for transferring address signals and associated control signals and the data interface for transferring data signals, wherein each of the data signals are associated with ones of the address signals, an interface control system to allow the address interface and the data interface to operate independently, comprising:

address storage means coupled to the second unit and to the address interface and including a plurality of address queue means, each of said address queue means for storing in any order within said address queue means, said address signals being predetermined associated ones of the address signals and associated control signals provided by the first unit to the second unit via the address interface during one or more address transfer operations;

data storage means independently operative of said address storage means, coupled to the second unit and to the data interface for storing data signals provided by the first unit to the second unit via the data interface during one or more data transfer operations, said one or more data transfer operations being performed independently to said one or more address transfer operations; and

routing means coupled to said address storage means and to said data storage means for associating each of said stored data signals with an associated one of said plurality of address queue means which stores the associated ones of the address signals.

11. The interface control system of claim 10, wherein said address storage means includes correlation means for correlating said associated ones of said stored data signals to the associated ones of the address signals within said associated one of said plurality of address queue means.

12. The interface of claim 10 wherein said correlation means includes means for enabling the storing of pointers within said each of said plurality of address queue means, wherein each of said pointers is indicative of an address within said data means at which said associated ones of said stored data signals are stored.

13. The interface control system of claim 11, and further including a plurality of priority means each coupled to a different respective one of said plurality of address queue means for selecting ones of said stored address signals for processing by the second unit based on a predetermined priority algorithm.

14. The interface control system of claim 13 wherein each of said priority means includes means for blocking from selection for processing ones of said stored address signals that are associated with data signals until after said correlation means correlates the associated data signals to said ones of said stored address signals.

15. The interface control system of claim 10, wherein the control signals indicate, for the associated address signals, a selectable type of memory operation to be performed using the associated address signals, and wherein each of said address queue means stores said predetermined ones of the address signals based on said selectable type of memory operation.

16. The interface control system of claim 10, and further including data interface control means coupled to said data storage means for allowing said ones of said stored data signals to be stored by said data storage means an indeterminate amount of time prior to the time one of said address queue means receives the associated ones of said address signals.

17. The interface control system of claim 10 and further including address interface control means coupled to said address storage means for allowing any of said address queue means to store address signals which are associated with data signals an indeterminate amount of time prior to the time the associated ones of the data signals are received by said data storage means.

18. The interface control system of claim 16 wherein the address interface is bi-directional, and wherein said data interface control means includes means to allow said data storage means to receive data signals from said first unit via said data interface simultaneously with the second unit providing address signals to the first unit via the address interface.

19. The interface control system of claim 17 wherein the data interface is bi-directional, and wherein said address interface control means includes means to allow said address storage means to receive address signals from said first unit via said address interface simultaneously with the second unit providing data signals to the first unit via the address interface.

20. The interface control system of claim 10 wherein each of said plurality of address queue means includes means for receiving address signals during a predetermined maximum number of address transfer operations prior to ones of said received address signals being associated with ones of said stored data signals.

21. In a data processing system in which a first unit is coupled to a second unit via a high-speed direct interface, wherein the interface includes both an address interconnection for transferred address signals and a data interconnection for transferring data signals, and wherein the second unit includes a plurality of first storage devices for storing the transferred address signals and a second storage device for storing the transferred data signals, a method of maximizing bandpass on the interface, comprising the steps of:

(a) performing one or more address transfer operations via the address interconnection, wherein each of said address transfer operations transfers address signals from the first unit to the second unit;

(b) associating each of said address transfer operations with an associated one of the plurality of first storage devices;

(c) storing the address signals for each of said address transfer operations in said associated one of the plurality of first storage devices in any order within said associated one of the plurality of first storage devices, said address signals being;

(d) performing one or more data transfer operations via said data interface, wherein each of said data transfer operations transfers data signals from the first unit to the second unit, and wherein each of said data transfer operations is performed independently of, and asynchronously to, any of said address transfer operations, and wherein each of said data transfer operation is associated with a associated one of said address transfer operations; and

(e) associating each of said one or more data transfer operations with a one of said plurality of first storage devices which is associated with said associated one of said address transfer operation.

22. The method of claim 21, and further including the step of

(f) correlating each of said one or more data transfer operations with said associated one of said one or more address transfer operations.

23. The method of claim 21, wherein the second unit further includes a data-before- address circuit, and step (d) further includes the steps of

(d1) determining if each of said one or more data transfer operations is performed prior to said associated one of said one or more address transfer operations;

and

(d2) temporarily storing data signals transferred during a data transfer operation performed prior to said associated one of said one or more address transfer operation until said associated one of said one or more address transfer operations is performed.

24. The method of claim 21, and further including the step of storing in the second storage device data signals transferred during said one or more data transfer operations.

25. The method of claim 24, wherein said step of storing data signals further includes the step of generating for each of said one or more data transfer operations respective pointer signals indicative of an address in the second storage device at which data signals for said each of said one or more data transfer operations are stored.

26. The method of claim 25, wherein step (f) includes the step of storing said respective pointer signals for any of said one or more data transfer operations in said associated one of said first storage devices along with the address signals for said associated one of said one or more address transfer operations.

27. The method of claim 22, and further including the step of selecting for processing by the second unit the address signals associated with one of said one or more address transfer operations based on a predetermined priority algorithm, and wherein said predetermined priority algorithm blocks for processing all address transfer operations which is associated with a data transfer operation that has not yet been performed.

28. The method of claim 27, wherein the second unit includes a plurality of resources, wherein each of said one or more address transfer operations is requesting access to one of said resources, and wherein said predetermined priority algorithm selects for processing one of said one or more address transfer operations based on availability of requested ones of said resources.

29. For use in a data processing system having a set of first units and a set of second units, wherein each first unit is capable of making requests to each second unit and each of the requests includes address signals and predetermined ones of the requests including data signals, an interface system for coupling one of said set of first units to one of said second units to transfer the requests from said one of said first units to said one of said second units, comprising:

an address interface coupling said one of said first units to said one of said second units to perform selected address transfer operations, each of said address transfer operations to transfer address signals associated with a respective one of the requests;

a plurality of address storage devices coupled to said address interface, each one of said plurality of address storage devices arranged to store address signals in any order within said plurality of address storage devices, said address signals being associated with predetermined ones of said address transfer operations;

a data interface coupling said one of said first units to said one of said second units to perform selected data transfer operations independently of said address transfer operations performed by said address interface, each of said data transfer operations to transfer data signals and each of said data transfer operations being associated with a respective one of said address transfer operations; and

a data routing logic circuit coupled to said data interface, coupled to said address interface, and coupled to each of said plurality of address storage devices, said data routing logic circuit to detect each occurrence of said data transfer operations and to associate said each occurrence of said data transfer operations to the one of said plurality of address storage devices coupled to store address signals for said respective one of said address transfer operations.

30. A data processing system having a set of first units and a set of second units, wherein each first unit is capable of making requests to each second unit and each of the requests includes address signals and predetermined ones of the requests including data signals, and wherein said requests are routed through an interface system comprising:

an address interface coupling one of said first units to one of said second units to perform selected address transfer operations, each of said address transfer operations to transfer address signals associated with a respective one of the requests;

a plurality of address storage devices coupled to said address interface, each one of said plurality of address storage devices arranged to store address signals in any order within said plurality of address storage devices, said address signals being associated with predetermined ones of said address transfer operations;

a set of data interfaces coupling each one of said first units to each one of said second units to perform selected data transfer operations independently of said address transfer operations performed by said address interface, each of said data transfer operations to transfer data signals and each of said data transfer operations being associated with a respective one of said address transfer operations; and

data routing logic circuits coupled to each said data interface, coupled to each said address interface, and coupled to each of said plurality of address storage devices, said data routing logic circuit to detect each occurrence of said data transfer operations and to associate said each occurrence of said data transfer operations to the one of said plurality of address storage devices coupled to store address signals for said respective one of said address transfer operations.