Virtual register sets

• US 6,178,482 B1
• Filed: 11/03/1997
• Issued: 01/23/2001
• Est. Priority Date: 11/03/1997
• Status: Expired due to Term

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: BRECIS Communications Corp. (Marvell Technology Group Limited)
• Inventors: Sollars, Donald L.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Tran, Denise
• Application Number:
  US08/963,391
• Time in Patent Office: 1,177 Days
• Field of Search: 711/5, 711/3, 711/6, 711/109, 711/118, 711/129, 711/203, 711/214-215
• US Class Current: 711/129
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/463 Program control block organisation

Abstract

One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.

Claims

1. An apparatus comprising:

cache memory having first one or more cache lines of cache locations; and

one or more control units coupled to said cache memory that dynamically operate said first one or more cache lines of cache locations during a first time period as registers of a first register set, and during a second time period as registers of a second register set;

wherein said one or more control units include a mapping unit coupled to said cache memory that operates to map during said first time period a first operand register designator of a first instruction to a first cache address of a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and to map during the second time period a second operand register designator of a second instruction to the same first cache address of the same first cache location being dynamically operated as a second register of the second register set.

2. The apparatus as set forth in claim 1, wherein the first and second register sets are register sets of a first virtual register file.

3. The apparatus as set forth in claim 1, wherein the first and second register sets are register sets of a first and a second virtual register file respectively.

4. The apparatus as set forth in claim 3, wherein the first and second virtual register files are of the same architecture.

5. The apparatus as set forth in claim 3, wherein the first and second virtual register files are of different architectures.

6. The apparatus as set forth in claim 1, wherein the mapping unit comprises circuitry that operates to determine during the first time period a first offset based on said first operand register designation, and to apply the first offset to a first base address of said first one or more cache lines of cache locations to generate the first cache address corresponding to the first cache location, and operates to determine during the second time period the same first offset based on said second operand register designation, and to apply the same first offset to the same first base address of said first one or more cache lines of cache locations to generate the same first cache address.

7. The apparatus as set forth in claim 1, wherein said one or more control units include a mapping unit coupled to said cache memory that operates to map during said first time period a first operand register designator of a first instruction to a first address tag associated with a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and to map during the second time period a second operand register designator of a second instruction to the same first address tag associated with the same first cache location being dynamically operated as a second register of the second register set.

8. The apparatus as set forth in claim 1, wherein the apparatus further comprises a first arithmetic logic unit (ALU) coupled to said cache memory that operates to perform during the first time period a first arithmetic/logic operation specified by a first instruction, including at least either employment of a first source operand retrieved from a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set or providing a first destination operand for storage in said first cache location, and operates to perform during the second time period a second arithmetic/logic operation specified by a second instruction, including at least either employment of a second source operand retrieved from the same first of the first one or more cache lines of cache locations being dynamically operated as a second register of the second register set, or providing a second destination operand for storage in said first cache location.

9. The apparatus as set forth in claim 8, wherein the apparatus further comprises a second arithmetic logic unit (ALU) coupled to said cache memory that operates to perform during the first time period the first arithmetic/logic operation specified by the first instruction, further including at least either employment of a third source operand retrieved from a second of the first one or more cache lines of cache locations being dynamically operated as a third register of a third register set or providing a third destination operand for storage in said second cache location, and operates to perform during the second time period the second arithmetic/logic operation specified by the second instruction, further including at least either employment of a fourth source operand retrieved from the same second of the first one or more cache lines of cache locations being dynamically operated as a fourth register of a fourth register set, or providing a fourth destination operand for storage in said second cache location.

10. The apparatus as set forth in claim 1, wherein

said cache memory further comprises first one or more cache tag storage locations corresponding to data storing cache locations of the first one or more cache lines; and

said one or more control units operate said cache memory as a write back cache, and store during the first time period, first one or more cache tags in the first one or more cache tag storage locations for the corresponding data storing cache locations of the first one or more cache lines, and during the second time, second one or more cache tags in the first one or more cache tag storage locations for the corresponding data storing cache locations of the first one or more cache lines, to effectuate said dynamic operation of said first one or more cache lines during the first time period as said first register set, and during the second time period as said second register set.

11. The apparatus as set forth in claim 1, wherein said cache memory further having second one or more cache lines of cache locations, and said one or more control units operate the second one or more cache lines of cache locations to cache data, concurrent with the first one or more cache lines being dynamically operated as registers of the first and second register sets.

12. A method comprising:

a) during a first time period, operating first one or more cache lines of cache locations as registers of a first register set to execute a first instruction; and

b) during a second time period, operating the same first one or more cache lines of cache locations as registers of a second register set to execute a second instruction;

wherein

step (a) comprises mapping during said first time a first operand register designator of the first instruction to a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and

step (b) comprises mapping during the second time period a second operand register designator of the second instruction to the same first of the first one or more cache lines of cache locations being dynamically operated as a second register of the second register set.

14. The method as set forth in claim 12, wherein the method further comprises the steps of:

(c) at the beginning of said first time period, storing first one or more cache tags for the first one or more cache lines in a first one or more cache tag storage locations corresponding to data storing cache locations of the first one or more cache lines to set up said first one or more cache lines to be dynamically operated as said first register set, and

(d) at the beginning of said second time period, saving the stored contents of said first one or more cache lines using said stored first one or more cache tags, and storing second one or more cache tags for the first one or more cache lines in the first one or more cache tag storage locations to set up said first one or more cache lines to be dynamically operated as said second register set of the virtual register file.

15. The method as set forth in claim 12, wherein the method further comprises

the step (c) operating a second one or more cache lines of cache locations to cache data, concurrent with the first one or more cache lines being dynamically operated as registers of the first and second register sets.

13. A method comprising:

a) during a first time period, operating first one or more cache lines of cache locations as registers of a first register set to execute a first instruction;

b) during a second time period, operating the same first one or more cache lines of cache locations as registers of a second register set to execute a second instruction;

(c) during the first time period, performing a first arithmetic/logic operation specified by the first instruction, including at least either employment of a first source operand retrieved from a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set or providing a first designation operand for storage in said first cache location, and

(d) during the second time period, performing a second arithmetic/logic operation specified by a second instruction, including at least either employment of a second source operand retrieved from the same first of the first one or more cache lines of cache locations being dynamically operated as a second register of the second register set, or providing a second destination operand for storage in the same first cache location.

16. The method as set forth in claim 13, wherein the method further comprises the steps of:

(e) at the beginning of said first time period, storing first one or more cache tags for the first one or more cache lines in a first one or more cache tag storage locations corresponding to data storing cache locations of the first one or more cache lines to set up said first one or more cache lines to be dynamically operated as said first register set, and

(f) at the beginning of said second time period, saving the stored contents of said first one or more cache lines using said stored first one or more cache tags, and storing second one or more cache tags for the first one or more cache lines in the first one or more cache tag storage locations to set up said first one or more cache lines to be dynamically operated as said second register set of the virtual register file.

17. The method of claim 13, wherein the method further comprises the step (e) operating a second one or more cache lines of cache locations to cache data, concurrent with the first one or more cache lines being dynamically operated as registers of the first and second register sets.