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Virtual register sets

  • US 6,178,482 B1
  • Filed: 11/03/1997
  • Issued: 01/23/2001
  • Est. Priority Date: 11/03/1997
  • Status: Expired due to Term
First Claim
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1. An apparatus comprising:

  • cache memory having first one or more cache lines of cache locations; and

    one or more control units coupled to said cache memory that dynamically operate said first one or more cache lines of cache locations during a first time period as registers of a first register set, and during a second time period as registers of a second register set;

    wherein said one or more control units include a mapping unit coupled to said cache memory that operates to map during said first time period a first operand register designator of a first instruction to a first cache address of a first of the first one or more cache lines of cache locations being dynamically operated as a first register of the first register set, and to map during the second time period a second operand register designator of a second instruction to the same first cache address of the same first cache location being dynamically operated as a second register of the second register set.

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