Modular, hybrid processor and method for producing a modular, hybrid processor

• US 6,178,494 B1
• Filed: 09/23/1996
• Issued: 01/23/2001
• Est. Priority Date: 09/23/1996
• Status: Expired due to Term

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Virtual Computer Incorporated (Cloud Software Group)
• Inventors: Casselman, Steve M.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/717,752
• Time in Patent Office: 1,583 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/921, 395/800.37, 395/500.05, 395/500.13, 712/357, 706/921
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A method is disclosed for integrating a field programmable gate array (FPGA) with a microprocessor to form a single, multi-chip or stacked, hybrid processor module. The method includes the identification and parallel routing of selected I/O pins of the FPGA and microprocessor. The method further includes the identification and routing of control pins of the FPGA and microprocessor to a controller, and, the establishment of an interface between the controller, the FPGA and the microprocessor in order to develop a processor module for coordinated processing of data utilizing both the FPGA and microprocessor resources.

Claims

1. A method for integrating a field programmable gate array (FPGA) resource having a first set of defined input/output (I/O) ports with a data processor having a second set of defined I/O ports within a single module, comprising the steps of:

identifying I/O ports of the FPGA and processor operable in parallel;

identifying control ports of the FPGA and processor;

routing the control ports to a controller;

establishing a controller-to-FPGA (C;

F) interface through the control pins of the FPGA;

establishing a processor-to-controller (P;

C) interface through the control pins of the processor; and

,

logically connecting the C;

F and P;

C interfaces;

wherein the step of indentifying I/O ports operable in parallel comprises the steps of;

identifying non-control, non-power, and non-ground ports of the FPGA and processor,

determining whether the identified ports are bi-directional,

determining whether bi-directional, identified ports are tri-stable, and

routing in parallel bi-directional, tri-stable identified ports.

2. The method of claim 1, wherein the step of identifying I/O ports operable in parallel includes the steps of:

determining whether non-bi-directional, identified ports are input ports;

determining whether non-bi-directional, identified, input ports receive signals during operation which force a hardwired change of state of the processor; and

,

routing in parallel non-bi-directional, identified, input ports which are determined not to force a change of state of the processor.

3. The method of claim 1, wherein the step of identifying I/O ports operable in parallel includes the steps of:

determining whether non-bi-directional, identified ports are output ports;

determining whether non-bi-directional, identified, output ports are tri-statable; and

routing in parallel non-bi-directional, tri-statable, identified, output ports.