On-chip circuit and method for testing memory devices

• US 6,178,532 B1
• Filed: 06/11/1998
• Issued: 01/23/2001
• Est. Priority Date: 06/11/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ingalls, Charles L., Pierce, Kim M.
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): Lamarre, Guy J.
• Application Number:
  US09/096,279
• Time in Patent Office: 957 Days
• Field of Search: 714/718, 365/201, 365/200, 365/233
• US Class Current: 714/718
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal. When the test mode signal is active, the test control circuit operates in a first mode to transfer data on the data terminal into the storage circuit, and operates in a second mode to transfer data from the storage circuit to the memory cells in the array. The test control circuit then operates in a third mode to access data stored in the memory cells and in the storage circuit such that the error detection circuit compares the data stored in each addressed memory cell to the data initially transferred to that memory cell.

Claims

1. An on-chip test circuit included in an integrated circuit memory device, the memory device including a memory-cell array having a plurality of memory cells arranged in rows and columns and a data terminal adapted to receive a data signal, the test circuit comprising:

a test mode terminal adapted to receive a test mode signal;

a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active;

an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal; and

a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit at a first rate, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array at a second rate that is greater than the first rate, and operable in a third mode to activate the read test data signal and access data stored in the memory cells at a third rate that is greater than the first rate such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.

2. The test circuit of claim 1 wherein the test data storage circuit comprises:

a plurality of latch circuits each having a respective input and an output, each latch circuit storing a bit of data applied on its input and providing the stored data on an output;

a plurality of input and output switch circuits, each switch circuit including first and second signal terminals and a control terminal adapted to receive a respective address control signal, the first signal terminal of each input switch circuit coupled to the input of an associated latch circuit and the second signal terminals of all input switch circuits coupled together, and the first signal terminal of each output switch circuit coupled to the output of an associated latch circuit and the second signal terminals of all output switch circuits coupled together, and each switch circuit coupling its first signal terminal to the second signal terminal responsive to the address control signal;

an input addressing circuit including a plurality of NAND gates, each NAND gate having an output coupled to the control terminal of an associated input switch circuit, a first input coupled to receive the write test data signal, and a second input coupled to receive an address signal; and

an output addressing circuit including a plurality of NAND gates, each NAND gate having an output coupled to the control terminal of an associated output switch circuit, a first input coupled to receive the read test data signal, and a second input coupled to receive an address signal.

3. The test circuit of claim 1 wherein the error detection circuit comprises:

an XOR gate having an output, one input coupled to the array, and a second input coupled to the output of the test data storage circuit;

a NOR gate having one input coupled to the output of the XOR gate, a second input coupled to the test control circuit, and an output;

an RS flip-flop circuit including two cross-coupled NOR gates, the flip-flop including a set input coupled to the output of the NOR gate, a reset input coupled to the test control circuit, and an output on which the error signal is developed.

4. The test circuit of claim 1 wherein the memory-cell array includes M columns and the test data storage circuit stores M bits of data.

5. The on-chip test circuit of claim 1 wherein the second rate is substantially equal to the third rate.

6. The on-chip test circuit of claim 5 wherein the first rate is determined by an external clock signal and the second and third rates are determined by an internal clock signal that is derived from the external clock signal, the internal clock signal having a frequency that is greater than a frequency of the external clock signal.

7. An on-chip test circuit in an integrated circuit memory device, the memory device including a data terminal adapted to receive a data signal, and an array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data and having an associated address, comprising:

a test mode terminal adapted to receive a test mode signal;

an external clock terminal adapted to receive an external clock signal having a frequency;

a clock multiplier circuit having an input coupled to the external clock terminal, the multiplier circuit developing an internal clock signal on an output in response to the external clock signal, the internal clock signal having a frequency greater than the frequency of the external clock signal;

a test data storage circuit including an input, output, and terminals adapted to receive respective control signals, the test data storage circuit operable in a first mode responsive to the control signals to store bits of data applied on the input, and operable in a second mode responsive to the control signals to provide on its output the stored bits of data;

an error detection circuit having inputs coupled respectively to the array and the output of the test data storage circuit, the error detection circuit activating an error signal on an output when the compared data is unequal;

a switch circuit including a first terminal coupled to the data terminal, a second terminal coupled to the input of the test data storage circuit, a third terminal coupled to the array, and a fourth terminal coupled to the output of the error detection circuit, the switch circuit selectively coupling the first terminal to one of the second, third, and fourth terminals responsive to a control signal; and

a test control circuit coupled to the output of the clock multiplier circuit, the test mode terminal, the array, and the control terminal of the switch circuit, the test control circuit operable responsive to the internal clock signal when the test mode signal is inactive to couple the data terminal to the array, and operable when the test mode signal is active to develop control signals to couple the data terminal to the input of the test data storage circuit, transfer data applied on the data terminal into the test data storage circuit at a first rate determined by the external clock signal, transfer data stored in the test data storage circuit into memory cells in the array at a second rate determined by the internal clock signal, access the data in respective memory cells in the array and the data in the storage circuit that was initially transferred to the memory cell such that the error detection circuit compares these two bits of data at a third rate determined by the internal clock signal, and couple the output of the error detection circuit to the data terminal so that the error signal is developed on the data terminal.

8. The test circuit of claim 7 wherein the test data storage circuit comprises:

a plurality of latch circuits each having a respective input and an output, each latch circuit storing a bit of data applied on its input and providing the stored data on an output;

a plurality of input and output switch circuits, each switch circuit including first and second signal terminals and a control terminal adapted to receive a respective address control signal, the first signal terminal of each input switch circuit coupled to the input of an associated latch circuit and the second signal terminals of all input switch circuits coupled together, and the first signal terminal of each output switch circuit coupled to the output of an associated latch circuit and the second signal terminals of all output switch circuits coupled together, and each switch circuit coupling its first signal terminal to the second signal terminal responsive to the address control signal;

an input addressing circuit including a plurality of NAND gates, each NAND gate having an output coupled to the control terminal of an associated input switch circuit, a first input coupled to receive the write test data signal, and a second input coupled to receive an address signal; and

an output addressing circuit including a plurality of NAND gates, each NAND gate having an output coupled to the control terminal of an associated output switch circuit, a first input coupled to receive the read test data signal, and a second input coupled to receive an address signal.

9. The test circuit of claim 7 wherein the error detection circuit comprises:

an XOR gate having an output, one input coupled to the array, and a second input coupled to the output of the test data storage circuit;

a NOR gate having one input coupled to the output of the XOR gate, a second input coupled to the test control circuit, and an output; and

an RS flip-flop circuit including two cross-coupled NOR gates, the flip-flop including a set input coupled to the output of the NOR gate, a reset input coupled to the test control circuit, and an output on which the error signal is developed.

10. The test circuit of claim 7 wherein the memory-cell array includes M columns and the test data storage circuit stores M bits of data.

11. A memory device, comprising:

an address bus;

a control bus;

a data bus;

a terminal adapted to receive a test mode signal;

an address decoder coupled to the address bus;

a control circuit coupled to the control bus;

a read/write circuit coupled to the data bus;

a memory-cell array coupled to the address decoder and read/write circuit, the array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data; and

a test circuit coupled to the data bus, including,

a test data storage circuit including an input coupled to the data bus and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data bus when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,

an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and

a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data bus into the storage circuit at a first rate, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array at a second rate that is greater than the first rate, and operable in a third mode to activate the read test data signal and access data stored in the memory cells at a third rate that is greater than the first rate such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.

12. The memory device of claim 11 wherein each memory cell comprises:

an access transistor having a gate terminal coupled to a respective word line associated with each row of memory cells in the array, and a drain terminal coupled to one of a respective pair of complementary digit lines associated with each column of memory cells, and a source terminal; and

a capacitor having a first plate coupled to the source terminal, and a second plate coupled to receive a reference voltage.

13. The memory device of claim 11 wherein the second rate is substantially equal to the third rate.

14. The memory device of claim 13 wherein the first rate is determined by an external clock signal and the second and third rates are determined by an internal clock signal that is derived from the external clock signal, the internal clock signal having a frequency that is greater than a frequency of the external clock signal.

15. A test system for detecting defects in a memory device, comprising:

a memory device including,

address, data and control buses to which an address decoder, read/write circuit, and control circuit are coupled, respectively,

a terminal adapted to receive a test mode signal,

a memory-cell array coupled to the address decoder and read/write circuit, the array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data, and

a test circuit coupled to the data bus, including,

a test data storage circuit including an input coupled to the data bus and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data bus when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,

an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and

a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data bus into the storage circuit at a first rate, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array at a second rate that is greater than the first rate, and operable in a third mode to activate the read test data signal and access data stored in the memory cells at a third rate that is greater than the first rate such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell; and

a test device coupled to the address, data, and control buses of the memory device and to the test mode terminal, the test device activating the test mode signal to place the memory device into a test mode and thereafter transferring a predetermined test pattern of data over the data bus to the test circuit at the first rate, and detecting a defect in the memory device when the error signal goes active.

16. The test system of claim 15 wherein the test device sequentially applies separate predetermined test patterns of data which are sequentially stored in the test data storage circuit, the test device determining at least once whether the error signal is active after applying a respective test pattern and before applying a subsequent test pattern.

17. The test system of claim 15 wherein the test device applies an alternating bit pattern of test data which is stored in test data storage register.

18. The test system of claim 15 wherein the second rate is substantially equal to the third rate.

19. The test system of claim 18 wherein the test device applies an external clock signal that determines the first rate, and the second and third rates are determined by an internal clock signal that is derived from the external clock signal, the internal clock signal having a frequency that is greater than a frequency of the external clock signal.

20. A computer system, comprising:

a data input device;

a data output device; and

computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device having a data terminal adapted to receive a data signal, and a test circuit including a memory-cell array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data, the test circuit including,

a test mode terminal adapted to receive a test mode signal,

a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,

an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and

a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit at a first rate, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array at a second rate that is greater than the first rate, and operable in a third mode to activate the read test data signal and access data stored in the memory cells at a third rate that is greater than the first rate such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.

21. A method for detecting defective memory cells in an array including a plurality of memory cells in an integrated circuit memory device, the memory device including data terminals adapted to receive data, the method comprising the steps of:

placing the memory device in a test mode;

storing in a test data storage circuit contained in the memory device at a first rate a plurality of bits of test data applied on the data terminals;

transferring the stored test data from the test data storage circuit to the memory cells at a second rate that is greater than the first rate;

comparing the test data stored in each of the memory cells to the corresponding test data initially transferred to the memory cell, the comparing being performed at a third rate that is greater than the first rate; and

detecting an error in a memory cell when the step of comparing indicates the data stored in the memory cell does not equal the test data transferred to the memory cell.

22. The method of claim 21 wherein the step of storing in the memory device a plurality of bits of test data applied on the data terminals includes the step of storing M bits of data where M equals the number of columns of memory cells in the memory-cell array.

23. The method of claim 21 wherein the step of storing in the memory device a plurality of bits of test data applied on the data terminals includes the step of sequentially storing bits of test data.

24. The method of claim 21 wherein the step of transferring the stored test data to the memory cells includes the step of sequentially transferring single bits of test data to respective memory cells.

25. The method of claim 21 wherein the step of storing in the memory device a plurality of bits of test data occurs at a first rate, and the steps of transferring the stored test data, storing the transferred test data, and comparing the test data all occur at a second rate greater than the first rate.

26. The method of claim 21 wherein the step of detecting occurs once every N times the step of comparing occurs.

27. The method of claim 21 wherein the first rate is determined by a first clock signal and the second and third rates are determined by a second clock signal that is derived from the first clock signal.

28. A method for testing a memory device including a memory-cell array having a plurality of memory cells, the memory device including a data terminal adapted to receive data, a clock terminal adapted to receive an external clock signal having a frequency, an internal clock node on which is developed an internal clock signal having a frequency greater than the external clock signal, the memory device further including a test data storage circuit coupled to the internal clock node which stores a plurality of bits of data, the method comprising the steps of:

applying test data sequentially on the data terminal;

storing the test data applied on the data terminal in the test data storage circuit at a rate determined by the external clock signal;

transferring test data in a predetermined sequence from the test data storage circuit to respective addressed memory cells at a rate determined by the internal clock signal;

accessing a memory cell;

accessing the data in the storage circuit that was transferred to the accessed memory cell;

comparing the test data stored in the accessed memory cell to the corresponding accessed data in the test data storage circuit at the rate determined by the internal clock signal;

detecting an error in a memory cell when the step of comparing indicates the data stored in the accessed memory cell does not equal the corresponding test data in the storage circuit;

activating an error signal on the data terminal when an error is detected; and

repeating the steps of accessing a memory cell through activating an error signal for each memory cell in the memory-cell array.

29. The method of claim 28 wherein the step of detecting occurs once every N times the step of comparing occurs.