High performance sub-system design and assembly

• US 6,180,426 B1
• Filed: 03/01/1999
• Issued: 01/30/2001
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US09/258,911
• Time in Patent Office: 701 Days
• Field of Search: 307/139, 437/209, 298/41, 438/14, 438/15, 438/110, 438/738, 257/320, 257/777, 257/203, 257/676, 257/723, 365/51
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted a second integrated circuit chip to physically and electrically connect the first integrated circuit chip to the second integrated circuit chip. The first integrated circuit chip has interchip interface circuits connected to the second integrated circuit chip to selectively communicate between internal circuits of the first and second integrated circuit chips or test interface circuits connected to the internal circuits of the first integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. The second integrated circuit chip has input/output interface circuitry to communicate with external circuitry connected to the second integrated circuit chip and to protect said second integrated circuit chip from electrostatic discharge voltages. Further, the second integrated circuit has interchip interface circuits connected to the first integrated circuit chip to communicate between the internal circuits of the first and second integrated circuit chips.

Claims

1. A method of forming a multiple integrated circuit chip structure comprising the steps of:

simultaneously but separately forming internal circuits on a first semiconductor wafer containing plural first integrated circuit chips and a second semiconductor wafer containing plural second integrated circuit chips;

simultaneously forming test circuits on the first wafer and the second wafer;

simultaneously forming interchip interface circuits on the first wafer and the second wafer, whereby forming said interchip interface circuit comprises the steps of;

forming an internal interface circuit for transferring electrical signals between a second integrated circuit chip to a first integrated circuit chip;

forming a mode select switch having a first terminal connected to an output of the internal interface circuit, a second terminal connected to the internal circuitry of the first integrated circuit chip;

forming a mode selector to selectively connect the output of the internal interface circuit to the internal circuitry of the first integrated circuit chip during normal operation and the output of the internal interface circuit to the test circuitry during test and burn-in;

forming input/output interface circuits on said second wafer;

contacting, stimulating, and examining a response of the test circuits on the first wafer and the test circuits and input/output interface circuits on the second wafer;

separating the first wafer into a plurality of separated first integrated circuit chips;

contacting with sockets, stimulating and burning-in the plurality of separated first integrated circuit chips for an extended period of time;

contacting, stimulating, and examining the plurality of separated first integrated circuit chips;

discarding defective first integrated circuit chips;

attaching each functioning chip of the first integrated circuit chips to a functioning second integrated circuit chip on the second wafer;

separating the second wafer into the plurality of second integrated circuit chips; and

contacting the input/output interface circuits, stimulating, and examining the response of the formed multiple integrated circuit chip structure.

2. The method of claim 1 wherein the attaching of each of the first integrated circuit chips to the second integrated circuit chips is accomplished by forming a area array of solder bumps between each of the first integrated circuit chips and the second integrated circuit chips.

3. The method of claim 1 wherein forming the test circuits comprises the steps of:

forming test interface circuits connected to external test circuitry to communicate with said external test circuitry and

forming ESD protection circuitry to protect said first and second integrated circuit chips from electrostatic discharge voltages.

4. The method of claim 1 wherein the first integrated circuit chip is fabricated using a first type of semiconductor process and the second integrated circuit chip is fabricated with a second type of semiconductor process that is not compatible with the first type of semiconductor process.

5. The method of claim 1 wherein the first integrated circuit chip is an array of memory cells and the second integrated circuit chip contains electronic circuitry formed with a process not compatible with a process of the array of memory cells.

6. The method of claim 1 wherein the second integrated circuit chip is an array of memory cells and the first integrated circuit chip contains electronic circuitry formed with a process not compatible with a process of the array of memory cells.

7. The method of claim 1 wherein contacting the test interface circuit comprises the step of temporarily connecting external test circuitry through an input/output pad to said test interface circuit.

8. The method of claim 1 wherein the interchip interface circuit is formed with no electrostatic discharge protection circuit.

9. The method of claim 1 wherein the internal interface circuit is formed with no ability to communicate with the external circuitry.

10. The method of claim 1 wherein the mode select switch comprises:

a first pass switch having a drain terminal connected to the internal circuits, a source terminal connected to an input/output pad connected to an attached integrated circuit chip, a first gate terminal connected to the mode selector, and a second gate terminal;

a second pass switch having a drain terminal connected to the internal circuits, a source terminal connected to the input/output pad connected to the attached integrated circuit chip, a first gate terminal, and a second gate terminal connected to the mode selector;

an inverter circuit having an input terminal connected to the mode selector and an output terminal connected to the second gate terminal of the first pass switch and the first gate of the second pass switch.

11. The method of claim 10 wherein the first and second pass switches are comprised of an NMOS transistor and a PMOS transistor connected in parallel with a gate of the NMOS transistor being the first gate terminal of the first and second pass switches and a gate of the PMOS transistor being the second gate terminal of the first and second pass switches.

12. The method of claim 1 wherein the mode select switch comprises:

an interchip input/output pad connected to a first logic state generator during normal operation;

a test input/output pad connected to a second logic state generator during testing procedures.