Bar field effect transistor

• US 6,180,441 B1
• Filed: 05/10/1999
• Issued: 01/30/2001
• Est. Priority Date: 12/13/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yue, John T., Fang, Peng, Buynoski, Matthew S., Liu, Yowjuang W.
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): RAO, SHRINIVAS H
• Application Number:
  US09/307,698
• Time in Patent Office: 631 Days
• Field of Search: 438/197, 438/259, 438/270, 438/271, 438/589
• US Class Current: 438/197
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Claims

1. A method of fabricating field-effect transistors, comprising the steps of:

providing a semiconductor layer having a first conductivity type;

forming a plurality of raised bars to extend above general surface of the semiconductor layer, each of the bars being elongated in a first direction and spaced apart by respective valleys in a second direction different from the first direction;

forming gate insulators on top surfaces of each said bars, and on bottoms of the valleys and on sidewalls of the bars which extend between the top surfaces and the valleys;

forming a conductive layer on each gate insulator layer so as to be disposed adjacent the top surfaces of the bars, and the bottoms of the valleys and the side walls;

patterning and etching the conductive layers to define an elongated continuous conductive gate which extends across the bars and into the valleys in the second direction, said gate being common to said field-effect transistors; and

implanting source regions and drain regions into portions of the semiconductor layer, each source and drain region being laterally adjacent to one another, with a channel region therebetween and adjacent to the bars, the side walls and bottoms of the valleys so as to be self-aligned to the conductive gate, a dopant selected for said step of implanting such that the source region and drain region are of second conductivity type opposite the first conductivity type.

2. The method of claim 1, wherein the elongated conductive gate is patterned and etched to have a width substantially less than a length of said bars.

3. The method of claim 1, and further comprising the steps of:

implanting the source region and the drain region to extend in the first direction beyond ends of the bars;

forming a contact hole at the end of at least one bar within the source region;

forming a contact hole at the end of at least one bar within the drain region; and

contacting each of the source region and the drain region at the ends of the bars such that contact will be made to the source region and the drain region through both sidewalls and bottoms of the respective contact holes.

4. The method of claim 1, and further comprising the steps of:

contacting the source region on the top surface of at least one bar so as to be spaced from the conductive gate; and

contacting the drain region on the top surface of at least one bar so as to be spaced from the conductive gate.

5. The method of claim 1, wherein said step of implanting further comprises the steps of:

implanting the dopant at a first angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent first ones of the sidewalls; and

implanting the dopant at a second angle to the sidewalls different from the first angle to introduce dopant into regions of the semiconductor layer adjacent second ones of the sidewalls.

6. The method of claim 5, and further comprising the step of implanting the dopant at an angle perpendicular to the general surface of the semiconductor layer.

7. The method of claim 1, and further comprising the steps of:

prior to said step of depositing the conductive layer, implanting dopant at a first angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent first ones of the sidewalls; and

prior to said step of depositing the conductive layer, implanting dopant at a second angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent second ones of the sidewalls.

8. The method of claim 7, and further comprising the step of prior to said step of depositing the conductive layer, implanting dopant at an angle perpendicular to the general surface of the semiconductor layer.

9. The method of claim 7, wherein a channel region spaces apart the drain region from the source region, the dopant implanted prior to said step of depositing the conductive layer being selected from dopant for prevention of channel region punch-through and dopant for adjusting the threshold voltage of the channel region.

10. A method of fabricating field effect transistors at a general surface of a semiconductor layer having a first conductivity type, comprising the steps of:

patterning and etching a plurality of trenches to extend downwardly from the surface of the semiconductor layer, the trenches being spaced apart from each other in a first direction, the trenches having bottom surfaces and defining therebetween a plurality of ridges with top surfaces of the ridges;

forming a gate insulator layer on the bottom surfaces of each of the trenches, the top surfaces of the ridges and the sidewalls;

forming conductive layers adjacent each of the gate insulators so as to be disposed insulatively adjacent the top surfaces of the ridges, the bottoms of the trenches and the side walls;

patterning and etching the conductive layers to form an elongated continuous conductive gate, that extend into the trenches and across the ridges in the first direction, said continuous gate being common to said field-effect transistors; and

implanting source regions and drain regions into portions of the semiconductor layer, each source region and drain region being laterally adjacent one another with a channel region therebetween and adjacent the bottom surfaces of the trenches the ridges and the sidewalls so as to be self-aligned to the conductive gate, a dopant for said step of implanting selected such that the source region and the drain region are of a second conductivity type opposite the first conductivity type.

11. The method of claim 10, and further comprising the step of patterning and etching the conductive gate so as to have a width that is less than the length of any of the trenches.

12. The method of claim 10, wherein said step of implanting further comprises the steps of:

implanting the dopant at a first angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent first ones of the sidewalls; and

implanting the dopant at a second angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent second ones of the sidewalls.

13. The method of claim 12, and further comprising the step of implanting the dopant at an angle perpendicular to the general surface of the semiconductor layer.

14. The method of claim 10, and further comprising the steps of:

prior to said step of forming the conductive layer, implanting dopant at a first angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent first ones of the sidewalls; and

prior to said step of forming the conductive layer, implanting dopant at a second angle to the sidewalls to introduce dopant into regions of the semiconductor layer adjacent second ones of the sidewalls.

15. The method of claim 14, and further comprising the step of prior to said step of depositing the conductive layer, implanting dopant at an angle perpendicular to the general surface of the semiconductor layer.

16. The method of claim 14, wherein a channel region spaces apart the drain region from the source region, the dopant implanted prior to said step of depositing the conductive layer being selected from dopant for prevention of channel region punch-through and dopant for adjusting the threshold voltage of the channel region.