Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed

• US 6,180,445 B1
• Filed: 04/24/2000
• Issued: 01/30/2001
• Est. Priority Date: 04/24/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chao-Chieh
• Primary Examiner(s): Tsai, H. Jay
• Application Number:
  US09/556,422
• Time in Patent Office: 281 Days
• Field of Search: 438/238, 438/381, 438/55, 438/26, 438/106-108
• US Class Current: 438/238
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of a high Q inductor that can be applied together with the mounting of flip chip semiconductor die on a substrate. The process of the invention starts with a semiconductor surface over which a layer of insulation and intra-metal dielectric have been deposited with interconnect patterns created in said layers of insulation and dielectric. A layer of low-K polyimide is deposited over the surface of the intra-metal dielectric, active circuits have previously been created in the substrate. After the layer of low-K polyimide has been deposited, a redistribution pattern is defined in the layer of low-K poly. Metal is deposited that forms the redistribution metal, the deposited layer of metal is planarized thereby forming the metal redistribution pattern. The inductor is next defined, the inductor is created on the surface of the layer of low-K polyimide. A layer of poly is deposited over the created inductor, back-end processing is then performed that creates openings for the BGA contact points that are to be established with the active devices in the substrate via BGA'"'"'s or other methods of interconnect.

Claims

1. A method of creating a high-Q inductor on a surface of a semiconductor substrate whereby said substrate is in addition used for mounting of flip chip semiconductor devices, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is divided into an active region adjacent to a region of electrical isolation adjacent to a region over which one or more inductors are to be created;

depositing a layer of insulation over a surface of said substrate;

depositing a layer of intra-metal dielectric over the surface of said layer of insulation;

creating a network of metal interconnects and metal points of contact in said layers of insulation including said layer of intra-metal dielectric whereby said network of metal interconnects and metal points of contact provide points of electrical contact in a surface of said layer of intra-metal dielectric whereby said points of electrical contact connect to points of electrical contact in a surface of said substrate;

depositing a layer of low-K polyimide over a surface of said substrate;

creating a pattern of redistribution vias in said layer of low-K polyimide;

creating a network of conductive interconnect lines in addition to creating one or more inductors on a surface of said layer of low-K polyimide;

depositing a layer of polyimide over a surface of said layer of low-K polyimide thereby including said network of conductive interconnect lines thereby furthermore including said one or more inductors on a surface of said layer of low-K polyimide; and

performing backend processing thereby interconnecting said flip chips to said network of conductive interconnect lines.

2. The method of claim 1 wherein said semiconductor surface contains:

an active surface region;

a surface region overlying which one or more inductors need to be created whereby said surface region overlying which one or more inductors need to be created is separated from said active surface region by a measurable distance when measured in a lateral direction along a surface of said substrate;

a region of electrical isolation that is located between said active region and said surface region overlying which one or more inductors need to be created;

points of electrical contact in said active surface region for connection of said active devices that are contained within said active surface region; and

points of electrical contact in said surface region overlying which one or more inductors need to be created for connection of said one or more inductors.

3. The method of claim 1 wherein said creating a pattern of redistribution vias in said layer of low-K polyimide comprises the steps of:

patterning said layer of low-K polyimide thereby creating openings in said layer of low-K polyimide whereby said openings align with said points of electrical contact in said active surface region for connection of said active devices with one or more active devices that have been provided in said active region of said substrate whereby said openings furthermore align with said points of electrical contact in said surface region overlying which one or more inductors need to be created for connection of said one or more inductors;

blanket depositing a layer of metal over a surface of said layer of low-K polyimide thereby filling said openings in said layer of low-K polyimide; and

planarizing said layer of metal essentially down to a surface of said layer of low-K polyimide thereby leaving said deposited metal in place inside said openings in said layer of low-K polyimide.

4. The method of claim 1 wherein said backend processing comprises the steps of:

patterning said layer of polyimide thereby creating openings in said layer of polyimide that align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate;

blanket depositing a layer of metal over a surface of said layer of polyimide; and

planarizing said layer of metal thereby establishing contact vias with one or more electrical contact points of one or more said active devices that have been provided in said active region of said substrate.

5. The method of claim 4 with the additional step of:

providing a solder mask over a surface of said layer of polyimide whereby said solder mask provides for solder connections that align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate;

placing contact balls over said solder mask whereby said contact balls align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate; and

electrically connecting one or more of said contact balls through the process of reflow of said placed contact balls whereby said contact balls make electrical contact with said one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate.

6. The method of claim 1 with additional processing steps, said additional processing steps to be performed prior to said depositing a layer of insulation over a surface of said substrate, said additional processing steps comprising:

performing an N+ implant into a surface of said substrate by implanting arson or phosphorous at an energy between about 25 and 75 KeV and a dose between about 5E11 and 5E13 atoms/cm³ thereby creating a region of N+ implant in a surface of said substrate whereby said region of N+ implant is located in said region of electrical isolation and immediately adjacent to said region over which one or more inductors are to be created and is furthermore immediately adjacent said latter region;

creating a trench for a first Shallow Trench Isolation in a surface of said substrate whereby said trench for a first Shallow Trench Isolation is located in said region of electrical isolation and immediately adjacent to said active region furthermore creating a trench for a second Shallow Trench Isolation in the surface of said substrate whereby said trench for a second Shallow Trench Isolation is adjacent to said N+ implant and underlies said surface region of said substrate over which one or more inductors are to be created; and

depositing a layer electrically isolating material in said trench for a first Shallow Trench Isolation and in said trench for a second Shallow Trench Isolation and planarizing a surface of said deposited layer of electrically isolating material down to a surface of said substrate.

7. The method of claim 6 with the addition processing steps of creating a liner of pad oxide on the inside surfaces of said trench for said first Shallow Trench Isolation and said trench for said second Shallow Trench Isolation to a thickness of between about 100 and 500 Angstrom through a thermal oxidation method at a temperature of about 900 degrees C. for a time period of about 10 to 20 minutes said additional processing steps to be performed prior to said depositing a layer electrically isolating material.

8. A method of creating a high-Q inductor on a surface of a semiconductor substrate whereby flip chip semiconductor devices are additionally mounted on said semiconductor substrate, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is provided with active devices and corresponding points of electrical contact to said active devices in addition to being provided with one or more surfaces over which one or more inductors are to be created with corresponding points of electrical contact to said one or more inductors;

depositing a layer of insulation over a surface of said substrate;

depositing a layer of intra-metal dielectric over a surface of said layer of insulation;

creating a network of metal interconnects and metal points of contact in said layers of insulation including said layer of intra-metal dielectric whereby said network of metal interconnects and metal points of contact provide points of electrical contact in a surface of said layer of intra-metal dielectric whereby said points of electrical contact connect to points of electrical contact in a surface of said substrate;

depositing a layer of low-K polyimide over a surface of said layer of intra-metal dielectric;

creating a pattern of redistribution vias in said layer of low-K polyimide further filling said pattern of redistribution vias with a conducting material whereby said pattern of redistribution vias interconnects with one or more points of electrical contact in a surface of said layer of intra-metal dielectric;

creating a network of conductive interconnect lines in addition to creating one or more inductors on a surface of said layer of low-K polyimide whereby said conductive interconnect lines align and connect with one or more points of electrical contact to said active devices whereby furthermore said one or more inductors align and connect with said points of electrical contact to said one or more inductors;

depositing a layer of polyimide over a surface of said layer of low-K polyimide thereby including said network of conductive interconnect lines thereby furthermore including said one or more inductors on a surface of said layer of low-K polyimide; and

performing backend processing thereby interconnecting said flip chips to said network of conductive interconnect lines.

9. A method of creating a high-Q inductor on a surface of a semiconductor substrate whereby flip chip semiconductor devices are additionally mounted on said semiconductor substrate, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is provided with active devices and corresponding points of electrical contact to said active devices in addition to being provided with one or more surfaces over which one or more inductors are to be created with corresponding points of electrical contact to said one or more inductors;

depositing a layer of insulation over a surface of said substrate;

depositing a layer of intra-metal dielectric over a surface of said layer of insulation;

creating a network of metal interconnects and metal points of contact in said layers of insulation including said layer of intra-metal dielectric whereby said network of metal interconnects and metal points of contact provide points of electrical contact in a surface of said layer of intra-metal dielectric whereby said points of electrical contact connect to points of electrical contact in a surface of said substrate;

depositing a layer of low-K polyimide over a surface of said layer of intra-metal dielectric;

creating a pattern of redistribution vias in said layer of low-K polyimide further filling said pattern of redistribution vias with a conducting material whereby said pattern of redistribution vias interconnects with one or more points of electrical contact in a surface of said layer of intra-metal dielectric;

creating a network of conductive interconnect lines in addition to creating one or more inductors on a surface of said layer of low-K polyimide whereby said conductive interconnect lines align and connect with one or more points of electrical contact to said active devices whereby furthermore said one or more inductors

align and connect with said points of electrical contact to said one or more inductors;

depositing a layer of polyimide over a surface of said layer of low-K polyimide thereby including said network of conductive interconnect lines thereby furthermore including said one or more inductors on a surface of said layer of low-K polyimide;

patterning said layer of polyimide thereby creating openings in said layer of polyimide that align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate;

blanket depositing a layer of metal over a surface of said layer of low-K polyimide;

planarizing said layer of metal thereby establishing contact vias with one or more electrical contact points of one or more said active devices that have been provided in said active region of said substrate;

providing a solder mask over a surface of said layer of polyimide whereby said solder mask provides for solder connections that align with one or more contact vias with one or more electrical contact points of one or more said active devices that have been provided in said active region of said substrate;

placing contact balls over said solder mask whereby said contact balls align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate; and

electrically connecting one or more of said contact balls through the process of reflow of said placed contact balls whereby said contact balls make electrical contact with said one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate.

10. The method of claim 9 with additional processing steps, said additional processing steps to be performed prior to said depositing a layer of insulation over a surface of said substrate, said additional processing steps comprising:

performing an N+ implant into a surface of said substrate by implanting arson or phosphorous at an energy between about 25 and 75 KeV and a dose between about 5E11 and 5E13 atoms/cm³ thereby creating a region of N+ implant in a surface of said substrate whereby said region of N+ implant is located in said region of electrical isolation and immediately adjacent to said region over which one or more inductors are to be created and is furthermore immediately adjacent said latter region;

creating a trench for a first Shallow Trench Isolation in a surface of said substrate whereby said trench for a first Shallow Trench Isolation is located in said region of electrical isolation and immediately adjacent to said active region furthermore creating a trench for a second Shallow Trench Isolation in the surface of said substrate whereby said trench for a second Shallow Trench Isolation is adjacent to said N+implant and underlies said surface region of said substrate over which one or more inductors are to be created; and

depositing a layer electrically isolating material in said trench for a first Shallow Trench Isolation and in said trench for a second Shallow Trench Isolation and planarizing a surface of said deposited layer of electrically isolating material down to a surface of said substrate.

11. A method of creating a high-Q inductor on a surface of a semiconductor substrate whereby flip chip semiconductor devices are additionally mounted on said semiconductor substrate, comprising the steps of:

providing a semiconductor substrate whereby a surface of said substrate is divided into an active region adjacent to a region of electrical isolation adjacent to and a region over which one or more inductors are to be created;

performing an N+ implant into a surface of said substrate thereby creating a region of N+ implant in a surface of said substrate whereby said region of N+ implant is located in said region of electrical isolation and immediately adjacent to said region over which one or more inductors are to be created and is furthermore immediately adjacent said latter region;

creating a trench for a first Shallow Trench Isolation in a surface of said substrate whereby said trench for a first Shallow Trench Isolation is located in said region of electrical isolation and immediately adjacent to said active region furthermore creating a trench for a second Shallow Trench Isolation in the surface of said substrate whereby said trench for a second Shallow Trench Isolation is adjacent to said N+ implant and underlies said surface region of said substrate over which one or more inductors are to be created;

depositing a layer of insulation over a surface of said substrate;

depositing a layer of intra-metal dielectric over the surface of said layer of insulation;

creating a network of metal interconnects and metal points of contact in said layers of insulation including said layer of intra-metal dielectric whereby said network of metal interconnects and metal points of contact provide points of electrical contact in a surface of said layer of intra-metal dielectric whereby said points of electrical contact connect to points of electrical contact in a surface of said substrate;

depositing a layer of low-K polyimide over a surface of said layer of intra-metal dielectric;

creating a pattern of redistribution vias in said layer of low-K polyimide further filling said pattern of redistribution vias with a conducting material;

creating a network of conductive interconnect lines in addition to creating one or more inductors on a surface of said layer of low-K polyimide whereby said conductive interconnect lines align and connect with one or more points of electrical contact to said active devices whereby furthermore said one or more inductors align and connect with said points of electrical contact to said one or more inductors;

depositing a layer of polyimide over a surface of said layer of low-K polyimide thereby including said network of conductive interconnect lines thereby furthermore including said one or more inductors on a surface of said layer of low-K polyimide;

patterning said layer of polyimide thereby creating openings in said layer of polyimide that align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate;

blanket depositing a layer of metal over a surface of said layer of polyimide;

planarizing said layer of metal thereby establishing contact vias with one or more electrical contact points of one or more said active devices that have been provided in said active region of said substrate;

providing a solder mask over a surface of said layer of polyimide whereby said solder mask provides for solder connections that align with one or more contact vias with one or more electrical contact points of one or more said active devices that have been provided in said active region of said substrate;

placing contact balls over said solder mask whereby said contact balls align with one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate; and

electrically connecting one or more of said contact balls through the process of reflow of said placed contact balls whereby said contact balls make electrical contact with said one or more points of electrical contact with one or more active devices that have been provided in said active region of said substrate.