Method for fabricating semiconductor device

• US 6,180,472 B1
• Filed: 07/27/1999
• Issued: 01/30/2001
• Est. Priority Date: 07/28/1998
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electronics Corp (Panasonic Holdings Corporation)
• Inventors: Akamatsu, Susumu, Kato, Yoshiaki, Shimizu, Tadami, Hibi, Toshitaka, Ueda, Takehiko, Shimazaki, Toyoyuki, Obata, Tatsuya
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/361,219
• Time in Patent Office: 553 Days
• Field of Search: 438/408, 438/301, 438/278, 438/344, 438/163, 438/519, 438/525, 438/595, 438/302, 438/303, 438/304, 257/408
• US Class Current: 438/303
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

After a gate insulating film, a gate electrode and an on-gate protective layer have been formed in this order on an Si substrate, lightly-doped source/drain regions are formed in the substrate. First and second sidewalls are formed on the sides of the gate electrode and then heavily-doped source/drain regions are formed by implanting dopant ions using these sidewalls as a mask. After the second sidewall has been selectively removed, pocket implanted regions are formed and an overall protective film is deposited. Thereafter, an interlevel dielectric film is deposited, contact holes are formed to reach the heavily-doped source/drain regions and then plug electrodes are formed. Since the second sidewall has already been removed when the overall protective film is deposited, the gap between adjacent gate electrodes is not completely filled in. Accordingly, it is possible to provide a method for fabricating a semiconductor device contributing to device miniaturization without causing a shortcircuit between the gate electrode and a contact member.

Claims

1. A method for fabricating a semiconductor device, comprising the steps of:

a) forming a gate insulating film, a gate electrode and an on-gate protective layer in this order on a semiconductor substrate;

b) implanting dopant ions into the semiconductor substrate using the gate electrode and the on-gate protective layer as a mask, thereby forming lightly-doped regions in the semiconductor substrate;

c) depositing a first insulating film and a masking film in this order over the substrate, the masking film being able to be etched selectively with respect to the first insulating film;

d) anisotropically etching the first insulating film and the masking film such that a first sidewall is formed on respective sides of the gate electrode and the on-gate protective layer by partially leaving the first insulating film thereon and that a second sidewall is formed on the first sidewall by partially leaving the masking film thereon;

e) implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first and second sidewalls as a mask, thereby forming heavily-doped regions in the semiconductor substrate;

f) selectively removing the second sidewall so as to leave the first sidewall after the step e) has been performed;

g) depositing a second insulating film over the substrate so as cover at least the on-gate protective layer and the first sidewall after the step f) has been performed;

h) depositing an interlevel dielectric film over the substrate after the step g) has been performed, the interlevel dielectric film being made of a material that is able to be etched selectively with respect to the second insulating film;

i) etching the interlevel dielectric film to form therein openings reaching the heavily-doped regions; and

j) filling the openings in with plug electrodes made of a conductive material.

2. The method of claim 1, wherein in the step c), an NSG film is formed as the first insulating film and a PSG or BPSG film is formed as the masking film.

3. The method of claim 2, wherein the step f) is performed by HF vapor phase etching.

4. The method of claim 1, further comprising the step of implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first sidewall as a mask, thereby forming pocket implanted layers in the semiconductor substrate between the steps f) and g).

5. The method of claim 1, further comprising, between the steps e) and f), the steps of:

forming a protective film over the semiconductor substrate, the protective film being used as a mask for a non-silicide region;

forming lightly-doped regions for preventing leakage under the heavily-doped regions using the protective film as a mask;

selectively removing part of the protective film, which covers a silicide region, so as to leave the other part thereof covering the non-silicide region; and

forming a silicide layer on the surface of the heavily-doped regions.

6. A method for fabricating a semiconductor device, comprising the steps of:

a) forming a gate insulating film, a gate electrode and an on-gate protective layer in this order on a semiconductor substrate;

b) depositing a first insulating film and a masking film in this order over the substrate, the masking film being able to be etched selectively with respect to the first insulating film;

c) anisotropically etching the first insulating film and the masking film such that a first sidewall is formed on respective sides of the gate electrode and the on-gate protective layer by partially leaving the first insulating film thereon and that a second sidewall is formed on the first sidewall by partially leaving the masking film thereon;

d) implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first and second sidewalls as a mask, thereby forming heavily-doped regions in the semiconductor substrate;

e) selectively removing the second sidewall so as to leave the first sidewall after the step d) has been performed;

f) implanting dopant ions into the semiconductor substrate using the gate electrode, the on-gate protective layer and the first sidewall as a mask, thereby forming lightly-doped regions in the semiconductor substrate after the step C) has been performed;

g) depositing a second insulating film over the substrate so as cover at least the on-gate protective layer and the first sidewall after the step f) has been performed;

h) depositing an interlevel dielectric film over the substrate after the step g) has been performed, the interlevel dielectric film being made of a material that is able to be etched selectively with respect to the second insulating film;

i) etching the interlevel dielectric film to form therein openings reaching the heavily-doped regions; and

j) filling the openings in with plug electrodes made of a conductive material.

7. The method of claim 6, wherein in the step b), an NSG film is formed as the first insulating film and a PSG or BPSG film is formed as the masking film.

8. The method of claim 7, wherein the step e) is performed by HF vapor phase etching.

9. The method of claim 6, further comprising the step of implanting dopant ions into the semiconductor substrate using the on-gate protective layer, the gate electrode and the first sidewall as a mask, thereby forming pocket implanted layers in the semiconductor substrate between the steps e) and g).

10. The method of claim 6, further comprising, between the steps d) and f), the steps of:

forming a protective film over the semiconductor substrate, the protective film being used as a mask for a non-silicide region;

forming lightly-doped regions for preventing leakage under the heavily-doped regions using the protective film as a mask;

selectively removing part of the protective film, which covers a silicide region, so as to leave the other part thereof covering the non-silicide region; and

forming a silicide layer on the surface of the heavily-doped regions.