Method for forming interconnect using dual damascene

• US 6,180,514 B1
• Filed: 11/12/1999
• Issued: 01/30/2001
• Est. Priority Date: 11/12/1999
• Status: Expired due to Fees

• Current Assignee: Lin, Wen-Jeng, Wen-Kuan Yeh
• Original Assignee: Lin, Wen-Jeng, Wen-Kuan Yeh
• Inventors: Lin, Wen-Jeng, Yeh, Wen-Kuan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/438,828
• Time in Patent Office: 445 Days
• Field of Search: 438/633, 438/620, 438/622, 438/634, 438/637, 438/638, 438/618, 438/687
• US Class Current: 438/633
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics

Abstract

A method for forming inter-metal dielectric is disclosed. The method normally includes the following steps. First of all, a semiconductor wafer is provided. Then, forming a first metal layer on a portion of the substrate is carried out. A first dielectric layer is formed on the first metal layer and the substrate. Consequentially a tantalum nitride layer is formed on the first dielectric layer. A first photoresist layer can be formed on the tantalum nitride layer, especially first photoresist layer has a first pattern defining a trench area located over the first metal layer, and has a second pattern defining an etch stop area. The tantalum nitride layer will be etched by the first photoresist layer. A second dielectric layer is formed over the etched tantalum nitride layer and the first dielectric layer. The second photoresist layer can be formed on the second dielectric layer, especially the second photoresist layer has a first pattern substantially aligned with the first pattern of the first photoresist layer, and has a second pattern substantially aligned with the second pattern of the first photoresist layer. Next, etching the second dielectric layer by the second photoresist layer can be achieved, portion of the first dielectric layer over the first metal layer is further etched by the first pattern of the first photoresist layer. Thus trenches are formed in the first dielectric layer and the second dielectric layer. Then the tantalum nitride layer is deposited into the trenches, especially barrier layer is formed on top surface of the trenches. A seed layer is formed on sidewalls of the etched first dielectric layer and the second dielectric layer. Sequentially, the trenches are filled by a second metal layer. Finally, the second metal layer is planarized to expose surface of said second dielectric layer.

Claims

1. A method for forming interconnect, comprising:

providing a semiconductor substrate;

forming a first metal layer on a portion of said substrate;

forming a first dielectric layer on said first metal layer and said substrate;

forming a barrier layer on said first dielectric layer;

forming a first photoresist layer on said barrier layer, wherein said first photoresist layer has a first pattern defining a trench area located over said first metal layer, and has a second pattern defining an etch stop area;

etching said barrier layer by the first photoresist layer;

forming a second dielectric layer over the etched barrier layer and the first dielectric layer;

forming a second photoresist layer on said second dielectric layer, wherein said second photoresist layer has a first pattern substantially aligned with the first pattern of said first photoresist layer, and has a second pattern substantially aligned with the second pattern of said first photoresist layer;

etching the second dielectric layer by the second photoresist layer, portion of said first dielectric layer over said first metal layer being further etched by the first pattern of the first photoresist layer, thereby trenches being formed in the first dielectric layer and the second dielectric layer;

depositing said barrier layer into said trenches, wherein said barrier layer being formed on top surface of said trenches;

forming a seed layer on sidewalls of the etched first dielectric layer and the second dielectric layer;

filling the trenches by a second metal layer, wherein said second metal layer is selected from the group consisting of a copper alloy layer and an aluminium—

copper alloy; and

planarizing said second metal layer to expose surface of said second dielectric layer.

2. The method according to claim 1, wherein said first photoresist layer has a thickness between about 5000 to 15000 angstroms.

3. The method according to claim 1, wherein said second photoresist layer has a thickness between about 5000 to 15000 angstroms.

4. The method according to claim 1, wherein said first dielectric layer is low-dielectric constant and has a thickness between about 4000 to 12000 angstroms.

5. The method according to claim 1, wherein said second dielectric layer is low-dielectric constant and has a thickness between about 4000 to 12000 angstroms.

6. The method according to claim 1, wherein said specified barrier comprises tantalum nitride.

7. The method according to claim 1, wherein said planarizing said second metal comprises chemical mechanical polishing.

8. A method for forming interconnect, comprising:

providing a semiconductor substrate;

forming a first metal layer on a portion of said substrate;

forming a first dielectric layer on said first metal layer and said substrate;

forming a tantalum nitride layer on said first dielectric layer;

forming a first photoresist layer on said tantalum nitride layer, wherein said first photoresist layer has a first pattern defining a trench area located over said first metal layer, and has a second pattern defining an etch stop area;

etching said tantalum nitride layer by the first photoresist layer;

forming a second dielectric layer over the etched tantalum nitride layer and the first dielectric layer;

forming a second photoresist layer on said second dielectric layer, wherein said second photoresist layer has a first pattern substantially aligned with the first pattern of said first photoresist layer, and has a second pattern substantially aligned with the second pattern of said first photoresist layer;

etching the second dielectric layer by the second photoresist layer, portion of said first dielectric layer over said first metal layer being further etched by the first pattern of the first photoresist layer, thereby trenches being formed in the first dielectric layer and the second dielectric layer;

depositing said tantalum nitride layer into said trenches, wherein said barrier layer being formed on top surface of said trenches;

forming a seed layer on sidewalls of the etched first dielectric layer and the second dielectric layer;

filling the trenches by a second metal layer; and

planarizing said second metal layer to expose surface of said second dielectric layer.

9. The method according to claim 8, wherein said first photoresist layer has a thickness between about 5000 to 15000 angstroms.

10. The method according to claim 8, wherein said second photoresist layer has a thickness between about 5000 to 15000 angstroms.

11. The method according to claim 8, wherein said first dielectric layer is low-dielectric constant (and has a thickness between about 4000 to 12000 angstroms).

12. The method according to claim 8, wherein said second dielectric layer is low-dielectric constant (and has a thickness between about 4000 to 12000 angstroms).

13. The method according to claim 8, wherein said second metal comprises aluminium—

copper alloy.

14. The method according to claim 8, wherein said planarizing said second metal comprises chemical mechanical polishing.