Method for forming vias in a low dielectric constant material

• US 6,180,518 B1
• Filed: 10/29/1999
• Issued: 01/30/2001
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Merchant, Sailesh Mansinh, Molloy, Simon John, Layadi, Nace, Roy, Pradip Kumar
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): PHAM, THANHHA S
• Application Number:
  US09/430,226
• Time in Patent Office: 459 Days
• Field of Search: 438/634, 438/623, 438/624, 438/637, 438/638, 438/639, 438/640, 438/672, 438/622, 438/666, 438/700, 438/702, 438/725, 438/734, 438/736, 438/738, 438/743, 438/744, 438/735
• US Class Current: 438/639
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.

Claims

1. A method for making a semiconductor device comprising the steps of:

forming a first conductive layer adjacent a substrate;

forming an etch stop layer on the first conductive layer;

forming a dielectric layer on the etch stop layer;

forming a via through the dielectric layer to expose the etch stop layer at the bottom and producing porous sidewalls; and

etching the exposed etch stop layer using an etchant, and while the etchant cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via.

2. A method according to claim 1, further comprising the step of etching polymeric material from the bottom of the via.

3. A method according to claim 2, wherein the etching is performed anisotropically.

4. A method according to claim 1, wherein the polymeric layer has a thickness less than about b 100 nm.

5. A method according to claim 1, wherein the etchant comprises at least one of monofluoromethane, difluoromethane and trifluoromethane.

6. A method according to claim 5, wherein the etchant further comprises argon and oxygen for controlling formation of the polymeric layer.

7. A method according to claim 1, wherein the dielectric layer comprises a material having a dielectric constant less than about 4.

8. A method according to claim 1, wherein the etch stop layer comprises silicon nitride.

9. A method according to claim 1, wherein the first conductive layer comprises copper.

10. A method according to claim 1, further comprising the steps of:

forming a barrier metal layer on the polymeric layer;

forming a seed layer on the barrier metal layer; and

forming a second conductive layer on the seed layer and contacting the first conductive layer.

11. A method according to claim 1, wherein the etching is performed using reactive ion etching.

12. A method for making a semiconductor device comprising the steps of:

forming a first conductive layer adjacent a substrate;

forming an etch stop layer on the first conductive layer;

forming a dielectric layer on the etch stop layer, the dielectric layer comprising a material having a dielectric constant less than about 4;

forming a via through the dielectric layer to expose the etch stop layer at the bottom and producing porous sidewalls;

etching the exposed etch stop layer using an etchant, and while the etchant cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via; and

etching polymeric material from the bottom of the via.

13. A method according to claim 12, wherein the step of etching polymeric material from the bottom of the via is performed anisotropically.

14. A method according to claim 12, wherein the polymeric layer has a thickness less than about 100 nm.

15. A method according to claim 12, wherein the etchant comprises at least one of monofluoromethane, difluoromethane and trifluoromethane.

16. A method according to claim 15, wherein the etchant further comprises argon and oxygen for controlling formation of the polymeric layer.

17. A method according to claim 12, wherein the etch stop layer comprises silicon nitride.

18. A method according to claim 12, wherein the first conductive layer comprises copper.

19. A method according to claim 12, further comprising the steps of:

forming a barrier metal layer on the polymeric layer;

forming a seed layer on the barrier metal layer; and

forming a second conductive layer on the seed layer and contacting the first conductive layer.

20. A method according to claim 19, wherein the second conductive layer comprises a metal plug.

21. A method according to claim 19, wherein the second conductive layer comprises at least one of copper, aluminum and alloys thereof.

22. A method according to claim 12, wherein the etchings are performed using reactive ion etching.

23. A method for forming a polymeric layer on porous sidewalls of a via in a semiconductor device comprising an etch stop layer on a first conductive layer and a dielectric layer on the first conductive layer, the method comprising the steps of:

forming the via through the dielectric layer to expose the etch stop layer at the bottom and producing porous sidewalls; and

etching the exposed etch stop layer using an etchant, and while the etchant cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via.

24. A method according to claim 23, further comprising the step of etching polymeric material from the bottom of the via.

25. A method according to claim 23, wherein the etching is performed anisotropically.

26. A method according to claim 23, wherein the polymeric layer has a thickness less than about 100 nm.

27. A method according to claim 23, wherein the etchant comprises at least one of monofluoromethane, difluoromethane and trifluoromethane.

28. A method according to claim 27, wherein the etchant further comprises argon and oxygen for controlling formation of the polymeric layer.

29. A method according to claim 23, wherein the dielectric layer comprises a material having a dielectric constant less than about 4.

30. A method according to claim 23, wherein the etch stop layer comprises silicon nitride.

31. A method according to claim 23, wherein the first conductive layer comprises copper.

32. A method according to claim 23, wherein the etching is performed using reactive ion etching.