Structure for increasing the maximum voltage of silicon carbide power transistors

• US 6,180,958 B1
• Filed: 02/07/1997
• Issued: 01/30/2001
• Est. Priority Date: 02/07/1997
• Status: Expired due to Term

• Current Assignee: United States Navy (U.S. Department Of Defense)
• Original Assignee: United States Navy (U.S. Department Of Defense)
• Inventors: Cooper, James Albert Jr.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/797,535
• Time in Patent Office: 1,453 Days
• Field of Search: 257/77, 257/328-331
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A silicon carbide insulated gate power transistor is disclosed that demonstrates increased maximum voltage. The transistor comprises a field effect or insulated gate transistor with a protective region adjacent the insulated gate that has the opposite conductivity type from the source for protecting the gate insulator material from the degrading or breakdown effects of a large voltage applied across the device.

Claims

1. A silicon carbide UMOS power transistor that demonstrates increased maximum voltage, said transistor comprising:

a metal oxide semiconductor, enhancement-type field effect transistor formed in silicon carbide and including a trench and a trench oxide on the walls and bottom of said trench;

said transistor having a source and a drain wherein both said source and said drain have the same conductivity type, said transistor further having a channel region with the opposite conductivity type from said source and said drain; and

an implanted protective region aligned beneath said trench oxide of said transistor that is directly grounded for protecting said trench oxide from the degrading or breakdown effects of a large voltage applied to the drain;

said implanted protective region being n-type when said source and drain are p-type and being p-type when said source and drain are n-type.

2. A silicon carbide UMOS power transistor that demonstrates increased maximum voltage, said transistor comprising:

an n-type silicon carbide substrate;

a p-type silicon carbide epitaxial layer on said n-type substrate;

an n-type well in said p-type epitaxial layer;

a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type substrate;

a gate oxide on the walls and bottom of said trench;

respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining a drain; and

a p-type silicon carbide region between said oxide and said n-type substrate that is directly grounded and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied to the drain.

3. A silicon carbide UMOS power transistor according to claim 2 wherein said p-type region is a grounded region.

4. A silicon carbide UMOS power transistor according to claim 2 wherein said p-type region is an implanted region.

5. A silicon carbide UMOS power transistor according to claim 2 wherein said p-type region is spaced sufficiently from said p-type epitaxial layer to minimize any current pinching effects between said p-type region and said p-type epitaxial layer.

6. A silicon carbide UMOS power transistor according to claim 2 wherein said ohmic contacts to said n-type well and said n-type substrate are selected from the group consisting of nickel and nickel alloys.

7. A silicon carbide UMOS power transistor according to claim 3 wherein said grounded p-type region is grounded through an ohmic contact selected from the group consisting of aluminum, aluminum alloys, and cobalt silicide.

8. A silicon carbide UMOS power transistor according to claim 2 wherein said n-type well and said n-type substrate are both doped with nitrogen, and wherein the dopant for said p-type epitaxial layer is selected from the group consisting of aluminum and boron.

9. A silicon carbide UMOS power transistor according to claim 2 wherein the silicon carbide has a polytype selected from the group consisting of 4H and 6H.

10. A silicon carbide UMOS power transistor according to claim 2 wherein said n-type substrate has a carrier concentration of about 2×

10¹⁶ cm<sup>−

3</sup>;

said p-type epitaxial layer has a carrier concentration of about 5×

10¹⁷ cm<sup>−

3</sup>; and

said p-type region beneath said oxide has a carrier concentration of about 5×

10¹⁷ cm<sup>−

3</sup>.

11. A silicon carbide UMOS power transistor that demonstrates increased maximum voltage, said transistor comprising:

an n-type silicon carbide substrate;

an n-type silicon carbide epitaxial layer on said n-type substrate;

a p-type epitaxial layer on said n-type epitaxial layer;

an n-type well in said p-type epitaxial layer;

a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type epitaxial layer;

a gate oxide on the walls and bottom of said trench;

respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining a drain; and

a p-type region between said oxide and said n-type epitaxial layer that is directly grounded and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied to the drain.

12. A silicon carbide UMOS power transistor according to claim 11 wherein said p-type region is a grounded region.

13. A silicon carbide UMOS power transistor according to claim 11 wherein said n-type substrate is more heavily doped than said n-type epitaxial layer.

14. A silicon carbide UMOS power transistor according to claim 11 wherein said n-type substrate has a carrier concentration of about 2×

10¹⁹ cm<sup>−

3</sup> and said n-type epitaxial layer has a carrier concentration of between about 2.5×

10¹⁵ cm<sup>−

3</sup> and 2×

10¹⁶ cm<sup>−

3</sup>.

15. A silicon carbide UMOS power transistor according to claim 11 wherein the silicon carbide has a polytype selected from the group consisting of 4H and 6H.

16. A silicon carbide UMOS power transistor according to claim 11 wherein said p-type epitaxial layer has a carrier concentration of about 5×

10¹⁷ cm<sup>−

3</sup>; and

said p-type region has a carrier concentration of about 5×

10¹⁷ cm<sup>−

3</sup>.

17. A silicon carbide UMOS power transistor according to claim 11 wherein said p-type region is an implanted region.

18. A silicon carbide UMOS power transistor according to claim 11 wherein the dopant for said p-type region is selected from the group consisting of aluminum and boron.

19. A silicon carbide UMOS power transistor according to claim 11 wherein said p-type region is spaced sufficiently from said p-type epitaxial layer to minimize any current pinching effects between said p-type region and said p-type epitaxial layer.

20. A silicon carbide UMOS power transistor according to claim 11 wherein said ohmic contacts to said n-type well and said n-type substrate are selected from the group consisting of nickel and nickel alloys.

21. A silicon carbide UMOS power transistor according to claim 12 wherein said grounded p-type region is grounded through an ohmic contact selected from the group consisting of aluminum, aluminum alloys and cobalt silicide.

22. A silicon carbide UMOS power transistor according to claim 11 wherein said n-type well, said n-type epitaxial layer, and said n-type substrate are all doped with nitrogen.

23. A silicon carbide UMOS power transistor according to claim 11 wherein said p-type epitaxial layer is doped with aluminum.

24. A silicon carbide insulated gate bipolar power transistor (IGBT) that demonstrates increased maximum voltage, said transistor comprising:

a p-type silicon carbide substrate;

an n-type silicon carbide epitaxial layer on said p-type substrate;

a p-type silicon carbide epitaxial layer on said n-type epitaxial layer;

an n-type well in said p-type epitaxial layer;

a gate trench extending through said n-type well and said p-type epitaxial layer and terminating in said n-type substrate;

a gate oxide on the walls and bottom of said trench;

respective ohmic contacts to said gate oxide for defining a gate, to said n-type well for defining a source, and to said substrate for defining an emitter; and

a p-type silicon carbide region between said oxide and said n-type epitaxial layer that is directly grounded and aligned with the bottom of said gate trench for protecting said oxide in said trench from the degrading or breakdown effects of a large positive voltage applied across said transistor.

25. A silicon carbide IGBT power transistor according to claim 24 wherein said p-type region is a grounded region.

26. A silicon carbide IGBT power transistor according to claim 24 wherein said p-type region is an implanted region.

27. A silicon carbide IGBT power transistor according to claim 24 wherein said p-type region is spaced sufficiently from said p-type epitaxial layer to minimize any current pinching effects between said p-type region and said p-type epitaxial layer.

28. A silicon carbide IGBT power transistor according to claim 24 wherein said ohmic contacts to said n-type well and said n-type substrate are selected from the group consisting of nickel and nickel alloys.

29. A silicon carbide IGBT power transistor according to claim 25 wherein said grounded p-type region is grounded through an ohmic contact selected from the group consisting of aluminum, aluminum alloys, and cobalt silicide.

30. A silicon carbide IGBT power transistor according to claim 24 wherein said n-type well and said n-type substrate are both doped with nitrogen, and wherein the dopant for said p-type epitaxial layer is selected from the group consisting of aluminum and boron.

31. A silicon carbide IGBT power transistor according to claim 24 wherein the silicon carbide has a polytype selected from the group consisting of 4H and 6H.