Semiconductor memory device and method for manufacturing the same

• US 6,180,973 B1
• Filed: 04/30/1998
• Issued: 01/30/2001
• Est. Priority Date: 03/11/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozaki, Tohru
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/069,853
• Time in Patent Office: 1,006 Days
• Field of Search: 257/301, 257/304, 257/305
• US Class Current: 257/305
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor
• CPC Class Codes: H10B 12/395 the transistor being vertical
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the substrate by the element isolation film, trenches formed in the element formation regions, respectively, capacitors each formed in a corresponding one of the trenches, each having a plate electrode formed of the substrate, a capacitor insulating film formed on the inner wall of the trench and a storage electrode filled in the trench with the capacitor insulating film disposed therebetween, transistors each formed in the element formation regions, and having a gate electrode which is formed to extend over the substrate and pass over the trench and the element formation region, a first impurity diffusion layer formed on one side of the gate electrode, a second impurity diffusion layer formed on the other side of the gate electrode, and channel regions formed on the element formation region on both sides of the trench below the gate electrode and respectively connected to the first and second impurity diffusion layers, connection electrodes for respectively connecting the storage electrodes to the first impurity diffusion layers, and signal transmission lines respectively connected to the second impurity diffusion layers.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate having a main surface;

an element isolation insulating film formed on said main surface of said semiconductor substrate and buried in a first trench;

a plurality of element formation regions each defined in an island form surrounded by said element isolation insulating film buried in said first trench;

a plurality of second trenches formed in said plurality of element formation regions to be surrounded thereby, respectively;

a plurality of capacitors formed in said plurality of second trenches, respectively, each of said capacitors having a plate electrode formed of said semiconductor substrate, a capacitor insulating film formed on an inner wall of each of said second trenches and a storage electrode formed in each of said second trenches with said capacitor insulating film disposed therebetween;

a plurality of transistors formed in said plurality of element formation regions, respectively, each of said transistors having,

a gate electrode formed having an upper surface and two opposite sides extending from the upper surface toward the semiconductor substrate, said gate electrode extending over said semiconductor substrate and passing over a portion of a corresponding one of said plurality of element formation regions and a corresponding one of said second trenches formed therein, said gate electrode being further disposed to be insulated from said storage electrode, the corresponding one of said plurality of element formation regions, and said semiconductor substrate,

a first impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on one of the opposite sides of said gate electrode,

a second impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on the other one of the opposite sides of said gate electrode, and

channel regions formed on said corresponding one of said plurality of element formation regions on opposing sides of the corresponding one of said second trenches below said gate electrode and respectively connected to said first and said second impurity diffusion layer;

a plurality of connection electrodes each connecting said storage electrode to said first impurity diffusion layer; and

a plurality of signal transmission lines each connected to said second impurity diffusion layer.

2. A semiconductor memory device according to claim 1, wherein each of said channel regions is formed to have a constant width from one end of corresponding one of said second trenches towards an outside thereof.

3. A semiconductor memory device according to claim 1, wherein each of said plurality of element formation regions is formed to project from a surface of said storage electrode and said gate electrode is formed to insulatively cover a surface of a projected portion of a corresponding one of said plurality of element formation regions.

4. A semiconductor memory device according to claim 3, wherein said channel regions are formed in an upper surface and side surfaces of said projected portion of each of said plurality of element formation regions below said gate electrode.

5. A semiconductor memory device according to claim 1, wherein said gate electrode is insulated from said storage electrode with a silicon oxide film and a silicon nitride film disposed therebetween.

6. A semiconductor memory device according to claim 1, wherein each of said plurality of transistors has two channel regions.

7. A semiconductor memory device according to claim 1, wherein each of said channel regions is sandwiched between said first trench and a corresponding one of said second trenches.

8. A semiconductor memory device comprising:

a semiconductor substrate;

an insulating layer formed on said semiconductor substrate;

a semiconductor region formed on said insulating layer;

an element isolation insulating film formed on said insulating layer to be connected thereto and buried in a first trench;

a plurality of element formation regions each defined in an island form surrounded by said element isolation insulating film buried in said first trench;

a plurality of second trenches formed in said plurality of element formation regions, respectively, to be surrounded thereby and to penetrate said insulating layer and reach said semiconductor substrate;

a plurality of capacitors each formed in said plurality of second trenches, respectively, each of said capacitors having a plate electrode formed of said semiconductor substrate, a capacitor insulating film formed on an inner wall of each of said second trenches and a storage electrode formed in each of said second trenches with said capacitor insulating film disposed therebetween;

a plurality of transistors formed in said plurality of element formation regions, respectively, each of said transistors having,

a gate electrode formed having an upper surface and two opposite sides extending from the upper surface toward the semiconductor substrate, said gate electrode extending over said semiconductor region and passing over a portion of a corresponding one of said plurality of element formation regions and a corresponding one of said second trenches formed therein, said gate electrode being further disposed to be insulated from said storage electrode, the corresponding one of said plurality of element formation regions, and said semiconductor region,

a first impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on one of the opposite sides of said gate electrode,

a second impurity diffusion layer formed on said corresponding one of said plurality of element formation regions on the other one of the opposite sides of said gate electrode, and

channel regions formed on said corresponding one of said plurality of element formation regions on opposing sides of the corresponding one of said second trenches below said gate electrode and respectively connected to said first and said second impurity diffusion layer;

a plurality of connection electrodes each connecting said storage electrode to said first impurity diffusion layer; and

a plurality of signal transmission lines each connected to said second impurity diffusion layer.

9. A semiconductor memory device according to claim 8, wherein each of said channel regions is formed to have a constant width from one end of corresponding one of said second trenches towards an outside thereof.

10. A semiconductor memory device according to claim 8, wherein each of said plurality of element formation regions is formed to project from a surface of said storage electrode and said gate electrode is formed to insulatively cover a surface of a projected portion of a corresponding one of said plurality of element formation regions.

11. A semiconductor memory device according to claim 10, wherein said channel regions are formed in an upper surface and side surfaces of said projected portion of each of said plurality of element formation regions below said gate electrode.

12. A semiconductor memory device according to claim 8, wherein said gate electrode is insulated from said storage electrode with a silicon oxide film and a silicon nitride film disposed therebetween.

13. A semiconductor memory device according to claim 8, wherein each of said plurality of transistors has two channel regions.

14. A semiconductor memory device according to claim 8, wherein each of said channel regions is sandwiched between said first trench and a corresponding one of said second trenches.