Memory cell arrangement with vertical MOS transistors and the production process thereof

• US 6,180,979 B1
• Filed: 09/08/1998
• Issued: 01/30/2001
• Est. Priority Date: 03/12/1996
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Willer, Josef, Hofmann, Franz, Krautschneider, Wolfgang
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/142,462
• Time in Patent Office: 875 Days
• Field of Search: 257/329, 257/330, 257/332, 257/335, 257/336, 257/344
• US Class Current: 257/329
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/40 having the source region and drain region on different levels, e.g. vertical channel

Abstract

In a memory cell arrangement which has vertical MOS transistors as memory cells, the information is stored by different threshold voltages of the transistors. For this purpose, dopant regions are formed for an information state by angled implantation or outdiffusion in the upper region of the channel region. The lower region of the channel region is in this case covered by an etching residue (9′) which is formed by masked spacer etching. The arrangement can be produced with an area requirement for each memory cell of 2 F² (F: minimum structure size).

Claims

1. A memory cell arrangement, comprising:

memory cells in a substrate said substrate having, at least in a region of a main area, semiconductor material which is doped with a first conductivity type, said memory cells including memory cells of a first type in which first predetermined information is stored and memory cells of a second type in which second predetermined information is stored, each memory cell having an MOS transistor which is vertical with respect to the main area;

the vertical MOS transistors having a gate dielectric and different threshold voltages depending on whether said first or said second predetermined information is stored therein;

strip-like trenches which substantially run in parallel in the substrate;

strip-like, doped regions, which are doped with a second conductivity type opposite to the first conductivity type, on a bottom of the trenches and on the main area between adjacent trenches;

a gate dielectric on sides of the trenches;

word lines which run transversely with respect to the trenches;

each of the vertical MOS transistors being respectively formed by two strip-like, doped regions adjoining a common side of one of the trenches, trench sides arranged in between the gate dielectric and one of the word lines;

each of said memory cells of said first type and of said second type having a dopant region in an upper region of the side of the trench, with an extent of said dopant region perpendicular to the main area being smaller than a depth of the trenches; and

in each of said memory cells of said second type, said dopant region being doped with said second conductivity type with an increased doping concentration compared to a doping concentration in said strip like, doped regions, to increase said threshold voltage to indicate storage of said second predetermined information.

2. The memory cell arrangement according to claim 1,

wherein spacing between adjacent trenches is equal to a width of the trenches; and

spacing between adjacent word lines is equal to a width of the word lines.

3. A memory cell arrangement as claimed in claim 1 wherein, in each of said memory cells of said first type, said dopant region is doped with said first conductivity type to decrease said threshold voltage to indicate storage of said first predetermined information.