Array of sidewall-contacted antifuses having diffused bit lines
First Claim
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1. An antifuse array formed on a semiconductor material of a first conductivity type, the array comprising:
- a plurality of spaced-apart bit lines formed in the semiconductor material that extend across the array, the bit lines having a second conductivity type;
a layer of insulation material formed on the semiconductor material over the bit lines, the layer of insulation material having a plurality of openings that expose a plurality of bit line regions on each bit line, the openings being arranged in rows and columns;
a plurality of spaced-apart contacts formed on the bit line regions such that each contact is connected to an exposed bit line region;
a layer of isolation material formed over the layer of insulation material and the contacts such that each contact has an exposed region;
a plurality of dielectric lines formed on the isolation material and the contacts so that a dielectric line is formed on the exposed region of each contact in a row of contacts, the dielectric lines extending across the array in a direction perpendicular to the bit lines; and
a plurality of conductive word lines formed on the plurality of dielectric lines to contact the dielectric lines so that a word line is formed on each dielectric line.
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Abstract
An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The array includes a plurality of spaced-apart bit lines which are formed in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word line includes a dielectric layer and a conductive layer.
16 Citations
15 Claims
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1. An antifuse array formed on a semiconductor material of a first conductivity type, the array comprising:
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a plurality of spaced-apart bit lines formed in the semiconductor material that extend across the array, the bit lines having a second conductivity type;
a layer of insulation material formed on the semiconductor material over the bit lines, the layer of insulation material having a plurality of openings that expose a plurality of bit line regions on each bit line, the openings being arranged in rows and columns;
a plurality of spaced-apart contacts formed on the bit line regions such that each contact is connected to an exposed bit line region;
a layer of isolation material formed over the layer of insulation material and the contacts such that each contact has an exposed region;
a plurality of dielectric lines formed on the isolation material and the contacts so that a dielectric line is formed on the exposed region of each contact in a row of contacts, the dielectric lines extending across the array in a direction perpendicular to the bit lines; and
a plurality of conductive word lines formed on the plurality of dielectric lines to contact the dielectric lines so that a word line is formed on each dielectric line. - View Dependent Claims (2, 3, 4, 5)
a plurality of spaced-apart first strips of insulation material formed on the surface of the semiconductor material, the first strips of insulation material having first thicknesses; and
a plurality of spaced-apart second strips of insulation material formed on the surface of the semiconductor material connected to the first strips of insulation material so that a second strip of insulation material is formed over each bit line, the second strips of insulation material having second thicknesses that are less than the first thicknesses.
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3. The array of claim 2 wherein the plurality of bit lines are implanted into the surface of the semiconductor material.
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4. The array of claim 3 wherein the contacts include doped polysilicon.
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5. The array of claim 4 wherein the conductive word line includes doped polysilicon.
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6. An antifuse array formed on a semiconductor material of a first conductivity type, the array having a plurality of sub-arrays, each sub-array comprising:
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a plurality of spaced-apart bit lines formed in the semiconductor material that extend across the array, the bit lines having a second conductivity type;
a layer of insulation material formed on the semiconductor material over the bit lines, the layer of insulation material having a plurality of openings that expose a plurality of bit line regions on each bit line, the openings being arranged in rows and columns;
a plurality of spaced-apart contacts formed on the bit line regions such that each contact is connected to an exposed bit line region;
a layer of isolation material formed over the layer of insulation material and the contacts such that each contact has an exposed region;
a plurality of dielectric lines formed on the isolation material and the contacts so that a dielectric line is formed on the exposed region of each contact in a row of contacts, the dielectric lines extending across the array in a direction perpendicular to the bit lines;
a plurality of conductive word lines formed on the plurality of dielectric lines to contact the dielectric lines so that a word line is formed on each dielectric line;
a plurality of drain regions formed in the semiconductor material so that a drain region is formed at each end of each bit line;
a plurality of gate oxide regions formed on the semiconductor material so that a gate oxide region is connected to each drain region;
a plurality of source regions formed in the semiconductor material so that a source region is connected to each gate oxide region; and
a pair of access lines formed on the gate oxide regions so that an access line is formed on each gate oxide region in a row of gate oxide regions. - View Dependent Claims (7, 8, 9, 10)
a plurality of spaced-apart first strips of insulation material formed on the surface of the semiconductor material; and
a plurality of spaced-apart second strips of insulation material formed on the surface of the semiconductor material connected to the first strips of insulation material so that a second strip of insulation material is formed over each bit line.
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8. The array of claim 7 wherein the plurality of bit lines are implanted into the surface of the semiconductor material.
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9. The array of claim 8 wherein the contacts include doped polysilicon.
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10. The array of claim 9 wherein the conductive material includes doped polysilicon.
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11. A method for programming a row of antifuses in an antifuse array formed on a semiconductor material of a first conductivity type, the array comprising:
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a plurality of spaced-apart bit lines formed in the semiconductor material that extend across the array, the bit lines having a second conductivity type;
a layer of insulation material formed on the semiconductor material over the bit lines, the layer of insulation material having a plurality of openings that expose a plurality of bit line regions on each bit line, the openings being arranged in rows and columns;
a plurality of spaced-apart contacts formed on the bit line regions such that each contact is connected to an exposed bit line region;
a layer of isolation material formed over the layer of insulation material and the contacts such that each contact has an exposed region;
a plurality of dielectric lines formed on the isolation material and the contacts so that a dielectric line is formed on the exposed region of each contact in a row of contacts, the dielectric lines extending across the array in a direction perpendicular to the bit lines; and
a plurality of conductive word lines formed on the plurality of dielectric lines to contact the dielectric lines so that a word line is formed on each dielectric line;
the method comprising the steps of;
applying a first voltage to the word line connected to the row of antifuses to be programmed; and
applying a second voltage to each bit line connected to each antifuse in the row of antifuses to be programmed. - View Dependent Claims (12, 13, 14, 15)
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Specification
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Current AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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Original AssigneeNational Semiconductor Corporation (Texas Instruments, Inc.)
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InventorsKalnitsky, Alexander, Bergemont, Albert
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Primary Examiner(s)CARROLL, JAMES J
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Application NumberUS09/234,007Time in Patent Office742 DaysField of Search257/530, 257/635, 257/754US Class Current257/530CPC Class CodesH01L 23/5252 comprising anti-fuses, i.e....H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
