Integrated circuit incorporating a programmable cross-bar switch

• US 6,181,159 B1
• Filed: 08/25/1998
• Issued: 01/30/2001
• Est. Priority Date: 05/06/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rangasayee, Krishna
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/139,960
• Time in Patent Office: 889 Days
• Field of Search: 326/39, 326/41, 326/47
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

An integrated circuit operable in a plurality of switching modes is disclosed. The integrated circuit includes a plurality of direct connectors and a programmable switch unit operable in a plurality of switching modes. The programmable switch unit has a plurality of bi-directional I/O ports selectively connected by way of programmable switch unit internal connectors. The integrated circuit also includes a programmable function unit directly connected to the programmable switch unit by way of the direct connectors. The programmable function unit is programmably configured to operate as required by a selected one of the plurality of switching modes. As required by the selected one of the plurality of switching modes, the programmable function unit directs the programmable switch unit to form internal connections using the programmable switch unit internal connectors such that that programmable switch unit passes signals between selected portions of the plurality of bi-directional I/O ports.

Claims

1. An integrated circuit operable in a plurality of switching modes, comprising:

a plurality of direct connectors;

a programmable switch unit operable in a plurality of switching modes, said programmable switch unit has a plurality of bi-directional I/O ports selectively connected by way of programmable switch unit internal connectors; and

a programmable function unit directly connected to said programmable switch unit by way of said direct connectors, wherein said programmable function unit directs said programmable switch unit to form internal connections using said programmable switch unit internal connectors as required by said selected one of said plurality of switching modes such that said programmable switch unit passes signals between selected portions of said plurality of bi-directional I/O ports.

2. An integrated circuit operable in a plurality of switching modes as recited in claim 1, wherein

said integrated circuit includes a plurality of programmable function units each independently programmable to operate in any of a plurality of modes as required by said selected one of said plurality of switching modes, and

wherein said integrated circuit includes a plurality of programmable switch units each made operable in a selected associated switch mode as required by said selected one of said plurality of switching modes.

3. An integrated circuit operable in a plurality of switching modes as recited in claim 2, wherein at least one of said programmed programmable function units directs at least one of said plurality of programmable switch units to operate in said selected associated switch modes.

4. An integrated circuit operable in a plurality of switching modes as recited in claim 3, wherein said integrated circuit is a programmable logic device.

5. An integrated circuit operable in a plurality of switching modes as recited in claim 4, wherein at least one of said programmable function units is a logic array block having logic elements for producing simple logic functions.

6. An integrated circuit operable in a plurality of switching modes as recited in claim 5, wherein at least one of said programmable function units is a memory array block having memory cells for storing data.

7. An integrated circuit operable in a plurality of switching modes as recited in claim 6, wherein said memory cell is a static random access memory (“

SRAM”

) cell.

8. An integrated circuit operable as a programmable switching device as recited in claim 7, further comprising a clock unit for producing appropriate clock signals.

9. A programmable logic device operable as a programmable switching device, comprising:

a plurality of interconnection lines;

a plurality of bi-directional input/output (I/O) ports, said bi-directional I/O ports can be connected to external circuitry;

a programmable function block that can be programmably connected to said plurality of bi-directional I/O ports via said plurality of interconnection lines; and

a programmable switch unit having a first plurality of I/O lines and a second plurality of I/O lines wherein a selected portion of said first plurality of I/O lines can be directed by said programmable function block as needed to connect with a selected portion of said second plurality of I/O lines such that signals can pass between said selected portions of said first and said second plurality of I/O lines as required by said programmable switching device.

10. A programmable logic device operable as a programmable switching device as recited in claim 9, wherein said programmable logic circuit includes a plurality of said programmable function blocks.

11. A programmable logic device operable as a programmable switching device as recited in claim 10, wherein at least one of said programmable function blocks has a plurality of logic cells interconnected by way of associated programmable logic cell connectors to form an array of logic cells, said array of logic cells being suitable for use in implementing desired logic functions.

12. A programmable logic device operable as a programmable switching device as recited in claim 11, wherein said array of logic cells is suitable for directing said programmable switch unit to connect said selected portions of said first and said second plurality of I/O lines.

13. A programmable logic device operable as a programmable switching device as recited in claim 12, wherein at least one of said programmable function blocks has a plurality of interconnected memory cells arranged to form a memory array, said memory array being suitable for implementing desired memory functions.

14. A programmable logic device operable as a programmable switching device as recited in claim 13, wherein said memory array is suitable for directing said programmable switch unit to connect said selected portions of said first and said second plurality of I/O lines.

15. A programmable logic device operable as a programmable switching device as recited in claim 13, further comprising a system clock device for providing an appropriate clock signal.

16. A programmable logic device operable as a programmable switching device as recited in claim 15, wherein said programmable switching unit comprises:

a plurality of horizontal data lines, each data line being connected to an associated one of said first plurality of selectable I/O lines and being connected to an associated one of said second plurality of selectable I/O lines,

a plurality of vertical data lines, and

an array of selectable programmable connectors, said array of selectable programmable connectors can be directed to couple selected ones of the plurality of vertical data lines to selected ones of the plurality of horizontal data lines such that selected ones of said first plurality of selectable I/O lines are electrically connected to selected ones of said second plurality of selectable I/O lines.

17. A programmable logic device operable as a programmable switching device as recited in claim 16, wherein said array of selectable programmable connectors can be directed by said memory array.

18. A programmable logic device operable as a programmable switching device as recited in claim 17 wherein a system clock is a phase locked loop (“

PLL”

) clock device.

19. A programmable logic device operable as a programmable switching device as recited in claim 18, wherein said memory cell is a static random access memory (“

SRAM”

) cell.