FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals

• US 6,181,163 B1
• Filed: 01/21/1999
• Issued: 01/30/2001
• Est. Priority Date: 01/21/1999
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantiss (Lattice Semiconductor Corporation)
• Inventors: Agrawal, Om P., Nguyen, Bai, Sharpe-Geisler, Bradley A., Chang, Herman M.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/235,351
• Time in Patent Office: 740 Days
• Field of Search: 326/37-41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB'"'"'s) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.

Claims

1. A field programmable gate array (FPGA) device comprising:

(a) a first plurality P1 of repeated logic units wherein;

(a.1) each said logic unit is user-configurable to acquire and process at least a second plurality P2 of input logic bits and to responsively produce result data having at least a third plurality P3 of output logic bits,

(a.2) said logic units are distributed among a plurality of horizontal rows and vertical columns, with each row of the plurality of rows having a fourth plurality P4 of said logic units and each column of the plurality of rows having a fifth plurality P5 of said logic units;

(b) a sixth plurality P6 of horizontal interconnect channels (HIC'"'"'s) correspondingly distributed adjacent to said horizontal rows of logic units, wherein;

(b.1) each said horizontal interconnect channel (HIC) includes at least P3 interconnect lines, and

(b.2) each said horizontal row of P4 logic units is configurably couplable to at least a corresponding one of the P6 HIC'"'"'s at least for acquiring input logic bits from the corresponding HIC or at least for outputting result data to the corresponding HIC;

(c) a seventh plurality P7 of vertical interconnect channels (VIC'"'"'s) correspondingly distributed adjacent to said vertical columns of logic units, wherein;

(c.1) each said vertical interconnect channel (VIC) includes at least P3 interconnect lines, and

(c.2) each said vertical column of P5 logic units is configurably couplable to at least a corresponding one of the P7 VIC'"'"'s at least for acquiring input logic bits from the corresponding VIC or at least for outputting result data to the corresponding VIC;

(d) an embedded memory subsystem, wherein said embedded memory subsystem includes;

(d.1) an eighth plurality P8 of memory blocks, and wherein;

(d.1a) each said memory block is embedded within one of said rows of logic units and is configurably couplable to the corresponding HIC of said row for transferring storage data by way of the corresponding HIC of that row of P4 logic units;

(d.1b) each of said memory blocks includes at least a first address-inputting section and/or a first control-inputting section for receiving respective address and control signals to which the memory block can respond; and

(d.1c) at least a first subset of said memory blocks defines a respective first, vertically-extending column; and

(e) a first memory controls-conveying interconnect channel (MCIC) extending adjacent to said first, vertically-extending column of memory blocks for acquiring at least one of memory address and memory control signals from other interconnect resources and for broadcasting and/or narrowcasting the acquired signals respectively to all or a programmably-defined subset of the memory blocks in the first, vertically-extending column of memory blocks.

2. A field programmable gate array device according to claim 1 wherein:

(c.1c) each said memory block is organized as a ninth plurality P9 of addressable sets of storage data bits, where each addressable set of storage data bits includes at least P3 bits, said P3 number corresponding to the P3 number of output logic bits producible by each said logic unit.

3. A field programmable gate array device according to claim 2 wherein:

(c.1c1) each of P2 and P3 is an integer equal to or greater than 4.

4. A field programmable gate array device according to claim 1 wherein:

(a.3) groups of said logic units are further wedged together such that each group of logic units defines a logic superstructure; and

(c.1c) groups of said memory blocks are also wedged together such that each group of memory blocks defines a memory superstructure that is configurably-couplable to a corresponding logic superstructure.

5. A field programmable gate array device according to claim 1 wherein:

(c.1b1) there are at least two of said columns of embedded memory; and

(c.2a) there are at least two of said Memory Controls-conveying Interconnect Channels (MCIC'"'"'s), and each respective MCIC is for supplying address and/or control signals to a respective one of the at least two columns of embedded memory.

6. A field programmable gate array device according to claim 5 wherein:

(c.1c) each said memory block has at least first and second data ports each for outputting storage data;

(c.1d) each said memory block has at least first and second address ports each for receiving address signals identifying the storage data to be output by a corresponding one of the at least first and second data ports; and

(c.1e) each MCIC includes first and second address-carrying components along which independent address signals may be respectively carried for application to respective ones of the first and second address ports of each memory block.

7. In a field programmable gate array device (FPGA) having a user-configurable interconnect network that includes a plurality of horizontal and vertical interconnect channels each with a diversified set of long-haul interconnect lines and shorter-haul interconnect lines, an embedded memory subsystem comprising:

(a) a plurality of multi-ported memory blocks each arranged adjacent to a horizontal interconnect channel (HIC) of the interconnect network;

wherein;

(a.1) each multi-ported memory block includes a first, independently-addressable data port and a second, independently-addressable data port;

(a.2) at least one group of said multi-ported memory blocks defines a respective first vertical memory column; and

(b) a first Memory Controls-conveying Interconnect Channel (MCIC) extending adjacent to said first vertical memory column for acquiring at least one of memory address and memory control signals from other interconnect resources and for selectively broadcasting or narrowcasting one or more of the acquired signals respectively to all or a programmably-defined subset of the memory blocks in the first vertical memory column.

8. In an FPGA device having a plurality of variable grain, configurable logic blocks (VGB'"'"'s) and interconnect resources including lines of diversified continuous lengths for interconnecting said VGB'"'"'s, an embedded memory subsystem comprising:

(a) a plurality of memory blocks wherein each memory block includes at least a first address and control signals inputting section for receiving respective first address and control signals to which the memory block responds; and

(b) a first Memory Controls-conveying Interconnect Channel (MCIC) extending adjacent to said plurality of memory blocks, said first MCIC being for acquiring at least one of memory address and memory control signals from other interconnect resources of the FPGA device and for selectively broadcasting or narrowcasting one or more of the acquired signals respectively to all or a programmably-defined subset of the memory blocks.

9. In an FPGA device having a configuration memory, a plurality of configurable logic blocks (CLB'"'"'s) and general interconnect resources for interconnecting said CLB'"'"'s in accordance with routing instructions stored in said configuration memory, an embedded memory subsystem comprising:

(a) a plurality of memory blocks wherein each memory block includes at least a first address inputting section and a controls inputting section for receiving respective first address signals and control signals to which the memory block responds; and

(b) a first Memory Controls-conveying Interconnect Channel (MCIC) coupled to said plurality of memory blocks, said first MCIC being for selectively acquiring, in accordance with acquisition instructions stored in said configuration memory, at least one of memory address and memory control signals from other interconnect resources of the FPGA device and for selectively broadcasting or narrowcasting, in accordance with transfer instructions stored in said configuration memory, one or more of the acquired signals respectively to all or a programmably-defined subset of the memory blocks.

10. A method for use in an FPGA device having a configuration memory, a plurality of variable grain blocks (VGB'"'"'s), diversified interconnect resources, and an embedded memory subsystem comprising a plurality of memory blocks situated for configurable coupling to the diversified interconnect resources, where the memory blocks each have at least one address input port and at least one data port, said method comprising the steps of:

(a) outputting a first address signal for conveyance by at least part of said interconnect resources;

(b) selectively acquiring the conveyed first address signal onto a Memory Controls-conveying Interconnect Channel (MCIC) that extends adjacent to at least a first plurality of the memory blocks; and

(c) broadcasting or narrowcasting, in accordance with transfer instructions stored in said configuration memory, one or more of the acquired signals respectively to all or a programmably-defined subset of the memory blocks adjacent to the MCIC.

11. The method of claim 10 wherein said step (a) of outputting the first address signal includes the substep of:

(a.1) transmitting the first address signal through a channels-interconnecting switchbox onto an interconnect channel that extends orthogonally across the MCIC.

12. The method of claim 10 wherein said step (a) of outputting the first address signal includes the substep of:

(a.1) transmitting the first address signal from a VGB onto an interconnect channel that extends adjacent to the signal-sourcing VGB and further extends orthogonally across the MCIC.

13. The method of claim 10 wherein said step (a) of outputting the first address signal includes the substep of:

(a.1) transmitting the first address signal from an IOB onto an interconnect channel that extends from the signal-sourcing IOB to cross orthogonally with the MCIC.

14. The method of claim 10 wherein said step (a) of outputting the first address signal includes the substep of:

(a.1) transmitting the first address signal from a NOR-line of an interconnect channel that extends by a plurality of IOB'"'"'s participating in a NOR function of the NOR-line, said NOR-line extending to cross orthogonally with the MCIC.

15. The method of claim 10 wherein said step (a) of outputting the first address signal includes the substeps of:

(a.1) transmitting the first address signal through a first of plural tristate drivers, where each of the tristate drivers has an output enabling terminal;

(a.2) providing an address-changing control signal that deactivates the output enabling terminal of the first tristate driver and enables the second of the tristate drivers.

16. A method for configuring an FPGA device having plural variable grain blocks (VGB'"'"'s), configurable interconnect resources, and an embedded memory subsystem comprising one or more memory blocks situated for configurable coupling via the configurable interconnect resources to the VGB'"'"'s, where the memory blocks each have at least one address input port for receiving supplied address bits, said method comprising the steps of:

(a) defining a first route through said interconnect resources from an address signal sourcing circuit of the FPGA device to the at least one address input port where said first route includes a Memory Controls-conveying Interconnect Channel (MCIC); and

(b) defining a second route through said interconnect resources between a data input/output circuit of the FPGA device and a data input/output port of the memory block.

17. A method for producing configuration signals for configuring an FPGA device having plural variable grain blocks (VGB'"'"'s), configurable interconnect resources, and an embedded memory subsystem comprising one or more memory blocks situated for configurable coupling via the configurable interconnect resources to the VGB'"'"'s, where the memory blocks are each situated adjacent to at least one Memory Controls-conveying Interconnect Channel (MCIC) for receiving supplied address and/or control bits from the MCIC, said method comprising the steps of:

(a) inputting a design definition;

(b) searching the input design definition for the presence of one or more memory modules, address-sourcing modules, and data-using modules that will cooperate to perform a memory read or memory write operation; and

(c) encouraging the creation in the configured FPGA of a shared signal route that transmits a shared address signal to the address input ports of plural memory blocks.