Circuit and method for a high gain, low input capacitance clock buffer

• US 6,181,182 B1
• Filed: 03/18/1999
• Issued: 01/30/2001
• Est. Priority Date: 03/18/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agilent Technologies Europe BV (Agilent Technologies, Inc.)
• Inventors: Nuber, Paul D., Stotz, Dan, Krzyzkowski, Richard A.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/272,042
• Time in Patent Office: 684 Days
• Field of Search: 327/256, 327/257, 327/294, 327/299, 327/291, 327/293, 327/258, 327/259, 326/29, 326/26, 326/27, 326/82, 326/83, 326/87
• US Class Current: 327/256
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A high gain, low input capacitance clock buffer includes a plurality of transistors configured to supply an inverted representation of an input reference signal by alternatively switching to provide the output. While either of the transistors is operating to switch the input clock signal, the other transistor is in a stable state. Furthermore, by using n-type FET'"'"'s, significant power reduction and space savings may be achieved.

Claims

1. An inverting clock buffer having high gain and low input capacitance, comprising:

a logic gate configured to receive a clock input signal and another signal that is an inverted and delayed representation of said clock input signal;

a first inverter configured to receive the output of said logic gate and supply an inverted output thereof;

a second inverter and a first transistor, each configured to receive as an input said clock input signal;

a third inverter and a second transistor, each configured to receive the output of said first inverter;

a fourth inverter configured to receive the output of said second inverter;

a third transistor configured to receive the output of said third inverter;

a fourth transistor configured to receive the output of said fourth inverter;

a fifth transistor configured to receive the output of said fourth inverter; and

a sixth transistor configured to receive the output of a fifth inverter, said fifth inverter configured to receive a first input from said first and second transistors and also configured to supply an output to a sixth inverter, said sixth inverter configured to supply a second input to said fifth inverter, said second input also reinforcing the output of said first and second transistors, said sixth transistor configured to supply as an output said inverted representation of said clock input signal.

2. The buffer of claim 1, wherein said third transistor is operational at a time when said fourth transistor is stable and said fourth transistor operates at a time when said third transistor is stable.

3. The buffer of claim 2, wherein said third transistor and said fourth transistor are n-type field effect transistors.

4. The buffer of claim 1, wherein said inverted representation of said clock input signal is switched between a low state and a high state.

5. The buffer of claim 1, wherein said third transistor and said fourth transistor are used to switch said output of said sixth transistor.

6. The buffer of claim 1, wherein said fifth transistor and said sixth transistor are configured to raise a voltage level of said output of said sixth transistor to a predetermined level.

7. The buffer of claim 1, wherein said clock input signal provides low input capacitance.