Using thick-oxide CMOS devices to interface high voltage integrated circuits

• US 6,181,193 B1
• Filed: 10/08/1999
• Issued: 01/30/2001
• Est. Priority Date: 10/08/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Coughlin, Terry C. Jr.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US09/415,862
• Time in Patent Office: 480 Days
• Field of Search: 327/108-112, 327/530, 327/534, 327/325, 327/391, 327/328, 361/56, 361/91
• US Class Current: 327/534
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Claims

1. A driver circuit for driving a bidirectional pad, comprising:

a diode connected from ground to said pad;

one or more series connected diodes connected from said pad to a first voltage supply;

a thick oxide PFET having a source connected to said first voltage supply, a drain connected to said pad, and an N-WELL;

a first thick oxide NFET having a drain connected to said pad, a gate connected to said first voltage supply, and a source;

a second thick oxide NFET having a drain connected to said source of said first NFET and a source connected to said ground;

a bias circuit for biasing said N-WELL of said PFET to the higher of either the voltage at said pad or said first voltage supply, and

an isolation circuit for turning off said PFET when said voltage at said pad rises above said first voltage supply.

2. A driver circuit according to claim 1, wherein:

the N-WELL includes (i) a series of thick oxide transistors connected together to form an N-WELL bias circuit, and (ii) an N-WELL node; and

the N-WELL bias circuit holds the N-WELL node at the first voltage when the pad voltage is less than or equal to said first voltage, and allows the N-WELL node to track the pad voltage when the pad voltage rises above said first voltage.