Amplitude and phase demodulation circuit for signals with very low modulation index

• US 6,181,198 B1
• Filed: 07/07/1998
• Issued: 01/30/2001
• Est. Priority Date: 07/18/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Poletto, Vanni, Sass, Dieter
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/111,289
• Time in Patent Office: 938 Days
• Field of Search: 340/825.54, 329/358, 329/361, 329/349, 329/353, 329/320, 329/318, 329/319, 329/317, 342/51, 455/337
• US Class Current: 329/358
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H03D 3/002 Modifications of demodulators to reduce interference by undesired signals H03D3/248 takes precedence

Abstract

An amplitude and phase demodulator circuit for signals with very low modulation index, including: amplifier circuitry adapted to amplify a modulated signal coming from a transmitter, the modulated signal being composed by a carrier and by a modulating component, circuitry adapted to cancel said carrier from said modulated signal; the circuitry adapted to cancel the carrier receiving in input the output signal of the amplifier circuitry and a sync signal coming from the transmitter, the output signal of the amplifier circuitry being delivered to receiver circuitry.

Claims

1. An amplitude and phase demodulator circuit for signals with very low modulation index, comprising:

amplifier means adapted to amplify a modulated signal coming from a transmitter, said modulated signal being composed by a carrier and by a modulating component;

means adapted to cancel said carrier from said modulated signal;

said means adapted to cancel the carrier receiving as an input the output signal of said amplifier means and a sync signal coming from said transmitter, the output signal of said amplifier means being delivered to receiver means;

wherein said means adapted to cancel said carrier comprises a synchronous resonator adapted to generate a carrier signal to be subtracted from said modulated signal output from said transmitter.

2. An amplitude and phase demodulator circuit according to claim 1, wherein said synchronous resonator receives as an input the output signal fedback from said amplifier means.

3. An amplitude and phase demodulator circuit according to claim 1, further comprising mixer means adapted to receive as an input the output signal from said synchronous resonator and said sync signal coming from the transmitter.

4. An amplitude and phase demodulator circuit according to claim 3, further comprising low-pass filter means arranged downstream of said mixer means, the output signal from said low-pass filter means being delivered to said receiver means.

5. An amplitude and phase demodulator circuit according to claim 1, wherein said means adapted to cancel the carrier from said modulated signal before amplifying it comprise first low-pass filter amplifying means receiving as an input a sample and hold signal derived from said modulated signal, and integrator means which receive as an input a feedback signal from said first low-pass filter amplifying means.

6. An amplitude and phase demodulator circuit according to claim 5, wherein said integrator means outputs a carrier DC level to be subtracted from said sample and hold signal delivered by sample and hold means, to derive a subtraction signal supplied to said first low-pass filter amplifying means.

7. An amplitude and phase demodulator circuit according to claim 6, wherein said sample and hold circuit receives as an input said sync signal from said transmitter and said modulated signal.

8. An amplitude and phase demodulator circuit according to claim 6, wherein said first low-pass filter amplifying means has an Av gain.

9. An amplitude and phase demodulator circuit according to claim 5, wherein said integrator means is a digital integrator.

10. An amplitude and phase demodulator circuit according to claim 9, wherein said circuit is fully integratable.

11. An amplitude and phase demodulator circuit according to claim 5, wherein said integrator means has a slow integration constant.

12. An amplitude and phase demodulator circuit according to claim 5, further comprising second low-pass filter amplifying means cascade-connected to said integrator means and a resistor is connected between the output of said second low-pass filter amplifying means and said integrator means.

13. An amplitude and phase demodulator circuit according to claim 12, wherein said integrator means, said first and second low-pass filter amplifying means each comprise an operational amplifier.

14. A method for amplitude and phase demodulating signals with very low modulation index comprising the steps of:

subtracting from a modulated signal, output from a transmitter, a carrier signal generated using a means adapted to cancel the carrier, to obtain a pre-processed signal;

amplifying said pre-processed signal; and

feeding back to said means adapted to cancel the carrier a signal obtained by said amplifying step, to derive an output signal to be delivered to a receiver;

wherein said step of using the means adapted to cancel the carrier includes using a synchronous resonator receiving as an input the signal derived from said amplifying step and a sync signal output from said transmitter.

15. A method according to claim 14, wherein said amplifying step is followed by a mixing step in which said output signal from the amplifying step and a sync signal output from said transmitter are added and the resulting signal is subjected to a low-pass filtering step.

16. A method according to claim 14, wherein the step of subtracting from the modulated signal said carrier signal is carried out by subtracting from a sample and hold signal a carrier DC level obtained by integrator means which receive as an input an output signal fedback from first low-pass filter amplifying means, said first low-pass filter amplifying means outputting a demodulated signal to be fed to said receiver means.

17. A method according to claim 16, wherein said sample and hold signal is derived by a sample and hold means connected to receive from said transmitter said sync signal and said modulated signal.

18. A method according to claim 16, wherein said integrator means has a slow integration constant.

19. A method according to claim 16, wherein said integrator means is a digital integrator.

20. A method according to claim 18, further comprising a step of speeding up the initial transient due to the slow integration constant of said integration means, said step of speeding up comprising modifying a pole of said integrator means.

21. A method according to claim 20, wherein said step of modifying said pole includes the step of adding second low-pass filter amplifying means cascade connected to said first low-pass filter amplifying means, and a resistor, said resistor being connected between the output of said second low-pass filter amplifying, means and said integrator means.

22. An amplitude and phase demodulator circuit, comprising:

a transmitter;

an amplifier adapted to amplify a modulated signal derived from said transmitter;

said modulated signal being composed by a carrier and a modulating component;

a synchronous resonator adapted to cancel the carrier from said modulated signal;

said synchronous resonator having one input connected to and for receiving the output signal, from said amplifier and another input connected to and for receiving a sync signal from said transmitter;

and a receiver connected to and for receiving the output signal from said amplifier.

23. An amplitude and phase demodulator circuit according to claim 22 wherein said synchronous resonator has an output for generating a carrier signal to be subtracted from said modulated signal output from said transmitter.

24. An amplitude and phase demodulator circuit according to claim 23 including a first mixer adapted to receive as an input the output signal from said synchronous resonator and said modulated signal from said transmitter.

25. An amplitude and phase demodulator circuit according to claim 24 including a second mixer adapted to receive as an input the output signal from said amplifier and said sync signal from the transmitter.

26. An amplitude and phase demodulator circuit according to claim 24 further comprising a low-pass filter disposed downstream of said first mixer, the output signal from said low-pass filter being coupled to said receiver.

27. An amplitude and phase demodulator circuit, comprising:

a transmitter;

an amplifier adapted to amplify a modulated signal derived from said transmitter;

said modulated signal being composed of a carrier and a modulating component;

a low pass filter amplifier receiving as an input a sample and hold signal derived from said modulating signal;

an integrator which receives as an input a feed-back signal from said low-pass filter amplifier;

and a receiver connected to and for receiving the output signal from said amplifier.

28. An amplitude and phase demodulator circuit according to claim 27 including a sample and hold circuit, wherein the integrator outputs a carrier DC level to be subtracted from said sample and hold signal delivered by a sample and hold circuit to derive a subtraction signal supplied to said low-pass filter amplifier.

29. An amplitude and phase demodulator circuit according to claim 28, wherein said sample and hold circuit receives as an input said sync signal from said transmitter and said modulated signal.

30. An amplitude and phase demodulator circuit according to claim 28, wherein said low-pass filter amplifier has an Av gain.

31. An amplitude and phase demodulator circuit according to claim 27, wherein said integrator is a digital integrator.

32. An amplitude and phase demodulator circuit according to claim 31, wherein said demodulator circuit is fully integratable.

33. An amplitude and phase demodulator circuit according to claim 27, wherein said integrator has a slow integration constant.

34. An amplitude and phase demodulator circuit according to claim 27, further comprising second low-pass filter amplifier, cascade-connected to said integrator, and a resistor is connected between the output of said second low-pass filter amplifying means said integrator.

35. An amplitude and phase demodulator circuit according to claim 34, wherein said integrator means, said first and second low-pass filter amplifiers each comprise an operational amplifier.

36. A method for amplitude and phase demodulating signals with very low modulation index, comprising the steps of:

providing a modulated signal, output from a transmitter;

providing a carrier signal;

subtracting the carrier signal from the modulated signal so as to cancel the carrier and obtain a pre-processed signal;

amplifying said pre-processed signal;

providing a receiver;

delivering the amplified signal to said receiver;

wherein said amplifying step is followed by a mixing step in which said output signal from the amplifying step and a sync signal output from said transmitter are added and the resulting signal is subjected to a low-pass filtering step.

37. A method according to claim 36, wherein the step of subtracting is carried out by subtracting from a sample and hold signal, a carrier DC level obtained by an integrator.

38. A method according to claim 37, including providing a sample and hold circuit connected to receive from said transmitter the sync signal and the modulated signal.

39. A method according to claim 38, wherein the integrator has a slow integration constant.

40. A method according to claim 39, wherein the integration is digital integration.

41. A method according to claim 40, further comprising a step of speeding up the initial transient due to the slow integration constant of the integrator.

42. A method according to claim 41, wherein the step of speeding up comprises the step of modifying a pole of the integrator.

43. A method according to claim 42, wherein said step of modifying said pole includes the step of adding second low-pass filter amplifier cascade connected to said first low-pass filter amplifier, and a resistor, said resistor being connected between the output of said second low-pass filter amplifier and said integrator.