Low cost chip size package and method of fabricating the same

• US 6,181,569 B1
• Filed: 06/07/1999
• Issued: 01/30/2001
• Est. Priority Date: 06/07/1999
• Status: Expired due to Fees

• Current Assignee: Kishore K. Chakravorty
• Original Assignee: Kishore K. Chakravorty
• Inventors: Chakravorty, Kishore K.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): Foster, David
• Application Number:
  US09/326,905
• Time in Patent Office: 603 Days
• Field of Search: 361/761, 361/760, 361/748, 361/750, 361/751, 361/762, 361/764, 361/777, 361/813, 257/737, 257/738, 257/684, 257/778, 257/779, 257/780, 257/676, 257/736, 257/700, 438/613, 438/614, 438/652, 438/666, 228/121.1, 228/121.2
• US Class Current: 361/761
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06505 Bonding areas having different materials
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14505 : Bump connectors having different materials
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 2201/0379 : Stacked conductors
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips. The first plurality of metal bumps can be deposited directly on the contact pads, with or without an underbump metalization layer, or on metal conductive traces over one or more dielectric layers.

Claims

1. A semiconductor chip package comprising:

a semiconductor chip having a plurality of contact pads;

a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads;

a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad;

a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace;

a first conductive bump formed in the second hole and extending above the second dielectric layer;

an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; and

a second conductive bump on top of and in electric contact with the first conductive bump.

2. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is located directly over a side edge of the semiconductor chip.

3. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is coplanar with a side edge of the semiconductor chip.

4. The semiconductor chip package of claim 1 wherein:

the first dielectric layer contains a first plurality of holes, each of the first plurality of holes overlying one of the contact pads;

a plurality of conductive traces extend from a location inside the first plurality of holes, respectively, each of the conductive traces being in electrical contact with one of the contact pads;

a second dielectric layer contains a second plurality of holes, each of the second plurality of holes overlying one of the traces and being lined with a conductive layer in electrical contact with the trace;

a plurality of first conductive bumps are formed in the second plurality of holes, respectively;

each of the plurality of first conductive bumps extends through the encapsulant layer; and

a plurality of second conductive bumps are formed on top of and in electric contact with the plurality of first conductive bumps, respectively.

5. The semiconductor chip package of claim 1 wherein the second conductive bump has a flat top portion that is coplanar with a surface of the encapsulant layer.

6. A semiconductor chip package comprising:

a semiconductor chip having a plurality of contact pads;

a first conductive bump in electrical contact with the contact pad;

an nonconductive encapsulant layer overlying the semiconductor chip and surrounding the conductive bump, the first conductive bump extending through the encapsulant layer; and

a second conductive bump on top of and in electric contact with the first conductive bump.

7. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is located directly over a side edge of the semiconductor chip.

8. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is coplanar with a side edge of the semiconductor chip.