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Multiple output power supply circuit for an ion engine with shared upper inverter

  • US 6,181,585 B1
  • Filed: 07/12/1999
  • Issued: 01/30/2001
  • Est. Priority Date: 07/12/1999
  • Status: Expired due to Term
First Claim
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1. A power supply circuit coupled to a bus having a bus input and a bus return comprising:

  • a square wave generator generating a first square wave signal and a second square wave signal, said first square wave signal and said second square wave signal are 180 degrees out of phase;

    a first primary winding of a first transformer having a first end and a second end;

    a first pulse width modulator;

    an upper inverter circuit coupled to said bus input and the first primary winding, said upper inverter circuit comprises a first switch coupled to said first end and a second switch coupled to said second end, said upper inverter circuit alternatively coupling said first end and said second end of said first primary winding to said bus input, said first switch and said second switch having a respective first control input and a second control input respectively coupled to said first square wave signal and said second square wave signal;

    a second pulse width modulator;

    a first lower inverter circuit coupled to said bus return and said first primary winding, said first lower inverter circuit comprises a third switch coupled to said first end and a fourth switch coupled to said second end, said third switch and said fourth switch selectively coupling said first primary winding to said bus return, said third switch and said fourth switch having a respective third control input and a fourth control input coupled to said first pulse width modulator;

    a second primary winding of a second transformer coupled to said upper inverter circuit, said second primary winding is electrically isolated from the first primary winding, said second primary winding having a third end coupled to said first switch and a fourth end coupled to said second switch; and

    a second lower inverter circuit coupled to said bus return and said second primary winding, said second lower inverter circuit comprises a fifth switch coupled to said third end and a sixth switch coupled to said fourth end, said fifth switch and said sixth switch selectively coupling said second primary winding to said bus return, said fifth switch and said sixth switch having a respective fifth control input and a sixth control input coupled to said second pulse width modulator.

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