Circuitry, apparatus and method for embedding quantifiable test results within a circuit being tested
First Claim
1. An integrated circuit, comprising a non-volatile storage device formed in a first address location reserved for receiving information as to a first test result magnitude obtained by performing a first electrical test upon the integrated circuit.
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Accused Products
Abstract
An integrated circuit, a programming mechanism and a method is provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.
27 Citations
21 Claims
- 1. An integrated circuit, comprising a non-volatile storage device formed in a first address location reserved for receiving information as to a first test result magnitude obtained by performing a first electrical test upon the integrated circuit.
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9. An apparatus for programming an integrated circuit, comprising:
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a programming mechanism adapted to address a first storage location within the integrated circuit reserved for receiving a first set of bits corresponding to a quantifiable test result obtained by performing a first electrical test upon the integrated circuit; and
a read mechanism adapted to read the first set of bits. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method for testing an integrated circuit, comprising:
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programming a first set of bits substantially permanently into the integrated circuit identifying the magnitude of a test result arising from a first testing operation; and
programming a second set of bits substantially permanently into the integrated circuit identifying a pre-defined limit against which the test result can be compared to indicate if the integrated circuit passes the first testing operation. - View Dependent Claims (18, 19, 20, 21)
programming a third set of bits substantially permanently into the integrated circuit identifying the magnitude of a test result arising from a second testing operation subsequent to the first testing operation; and
programming a fourth set of bits substantially permanently into the integrated circuit identifying a pre-defined limit against which the test result of the second testing operation can be compared to indicate if the integrated circuit passes the second testing operation.
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19. The method as recited in claim 18, wherein the second testing operation occurs subsequent to the first testing operation.
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20. The method as recited in claim 18, further comprising reading the first and third set of bits to determine a skew in the magnitude of the corresponding test results.
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21. The method as recited in claim 18, further comprising reading the second and fourth set of bits to determine a skew in the pre-defined limits against which the test results can be compared.
Specification