Multi-carrier transmission systems

• US 6,181,714 B1
• Filed: 06/01/1999
• Issued: 01/30/2001
• Est. Priority Date: 09/02/1996
• Status: Expired due to Term

• Current Assignee: Comcast Cable Communications LLC (Comcast Corporation)
• Original Assignee: Telia AB (Government of Norway)
• Inventors: Bahlenberg, Gunnar, Isaksson, Anders, Okvist, Goran, Ljunggren, Lis-Marie, Olsson, Lennart, Nordstrom, Tomas, Isaksson, Mikael, Isaksson, Lars-Ake, Johansson, Magnus, Bengtsson, Daniel, Tonvall, Harry, Hakansson, Siwert, Stefansson, Thomas, Wen, Ye, Ohman, Hans
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): JONES, PRENELL P
• Application Number:
  US09/147,749
• Time in Patent Office: 609 Days
• Field of Search: 370/491, 370/343, 370/206, 370/468, 370/207, 370/350, 370/500, 375/206, 375/222, 375/260, 375/221, 375/346, 375/480, 327/155, 327/156, 329/307, 329/325, 329/360
• US Class Current: 370/491
• CPC Class Codes: H04L 27/2614 Peak power aspects
• CPC Class Codes: H04L 27/2656 Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2675 Pilot or known symbols

Abstract

A multi-carrier transmission system using DMT. It is known to recover a receiver sample and clock from a reserved carrier, a pilot carrier having a fixed phase. A sampling clock oscillator in a receiver is then phase locked to the pilot carrier. Multi-carrier receivers, such as DMT receivers, are normally equipped with an FFT processor. A complex number representing the pilot carrier is then available from the FFT processor output. If an FFT processor is not available, a one frequency DFT processor can be provided to produce a complex estimate of the pilot carrier. In a DMT system, frame synchronization is handled separately from sampling clock synchronization, although the two processes are intimately related and frame synchronization must be acquired before sampling clock synchronization.

Claims

1. A receiver, for use with a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phase locking said receiver sampling clock to a pilot carrier, said receiver comprising:

a feedback loop configured to control an oscillator means, said feedback loop using a feedback signal representative of an argument estimate of said pilot carrier, wherein said feedback signal is derived from an approximation of an argument of a complex number representative of said pilot carrier, said approximation retaining a full resolution of said complex number, and wherein said feedback loop controls said oscillator means so that said pilot argument tends to zero.

2. A receiver as claimed in claim 1, wherein said feedback loop is configured to compensate for channel effects.

3. A receiver, as claimed in claim 1, wherein said oscillator means comprises a VCXO.

4. A receiver as claimed in claim 1, wherein said multi-carrier transmission system comprises a DMT transmission system.

5. A receiver as claimed in claim 1, wherein said multi-carrier transmission system comprises a DMT based VDSL system.

6. A receiver as claimed in claim 1, wherein said receiver includes pilot argument estimation means configured to produce said feedback signal, and wherein said pilot argument estimation means is connected to feedback controller means which is connected, via a D/A, to said oscillator means.

7. A receiver as claimed in claim 1, wherein said feedback signal functions as an equalizer parameter and causes said oscillator means to be adjusted to compensate for channel effects.

8. A receiver as claimed in claim 1, wherein said feedback signal is employed to equalize time variations in channel characteristics for a channel over which said pilot carrier is transmitted.

9. A receiver as claimed in claim 1, wherein said pilot carrier argument estimate is derived from an output of a FFT processor, by calculation.

10. A receiver as claimed in claim 1, wherein said pilot carrier argument estimate is derived from an output of a one-frequency DFT processor, by calculation.

11. A receiver as claimed in claim 1, wherein the imaginary part of said complex number is used as an approximation for said pilot carrier argument estimate.

12. A receiver as claimed in claim 1, wherein an approximation to said pilot carrier estimate is used which yields an extra large feedback signal at large deviations from zero argument.

13. A receiver as claimed in claim 12, wherein an approximation, A, to said estimate of said pilot carrier is used, wherein:

14. A receiver as claimed in claim 13, wherein K=2.

15. A transceiver comprising:

a transmitter; and

a receiver, for use with a multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is synchronized with a transmitter sampling clock by phase locking said receiver sampling clock to a pilot carrier, said receiver including

a feedback loop configured to control an oscillator means, said feedback loop using a feedback signal representative of an argument estimate of said pilot carrier, wherein said feedback signal is derived from an approximation of an argument of a complex number representative of said pilot carrier, said approximation retaining a full resolution of said complex number, and wherein said feedback loop controls said oscillator means so that said pilot argument tends to zero.

18. A transceiver as claimed in claim 15, wherein said multi-carrier transmission system comprises a DMT system.

19. A transceiver as claimed in claim 18, wherein said multi-carrier transmission system comprises a DMT based VDSL system.

16. A multi-carrier transmission system using orthogonal carriers, in which a receiver sampling clock is phase locked to a pilot carrier, wherein said multi-carrier transmission system comprises:

two transceivers, wherein each one of said two transceivers includes

a transmitter, and

a receiver, including

a feedback loop configured to control an oscillator means, said feedback loop using a feedback signal representative of an argument estimate of said pilot carrier,

wherein said feedback signal is derived from an approximation of an argument of a complex number representative of said pilot carrier, said approximation retaining a full resolution of said complex number, and wherein said feedback loop controls said oscillator means so that said pilot argument tends to zero.

17. A method for synchronizing a receiver clock with a transmitter clock, in which the transmitter transmits a pilot signal in a multi-carrier transmission system, said method comprising the steps of;

controlling a sampling clock in said receiver so that an argument of said pilot carrier converges to zero, and said pilot carrier argument is approximated by arithmetic operation on a complex number representative of said pilot signal.

20. A method for synchronizing a receiver sampling clock to a transmitter sampling clock in a multi-carrier transmission system using orthogonal carriers, in which said receiver sampling clock is synchronized with said transmitter sampling clock by phase locking said receiver sampling clock to a pilot carrier transmitted by said transmitter, said method comprising the steps of:

deriving a complex number representative of said pilot carrier;

deriving from said complex number an approximation of an argument of said pilot carrier;

using said approximation of said argument as a feedback signal to control said receiver sampling clock, so that said feedback signal tends to zero.

21. A method as claimed in claim 20, wherein said multi-carrier transmission system comprises a DMT transmission system.

23. A method as claimed in claim 20, wherein said feedback signal functions as an equalizer parameter and causes said sampling clock to be adjusted in a manner which compensates for channel effects.

24. A method as claimed in claim 20, further comprising the step of employing said feedback signal to equalize for time variations in channel characteristics in a channel over which said pilot carrier is transmitted.

25. A method as claimed in claim 20, further comprising the step of calculating said pilot carrier argument estimate from an output of a FFT processor.

26. A method as claimed in claim 20, further comprising the step of calculating said pilot carrier argument estimate from an output of a one-frequency DFT processor.

27. A method as claimed in claim 20, further comprising the step of using the imaginary part of said complex as an approximation for said pilot carrier argument.

28. A method as claimed in claim 20, further comprising the step of using an approximation to said complex number representing a pilot carrier estimation which yields an extra large feedback signal at large deviations from zero argument.

29. A method as claimed in claim 28, further comprising the step of:

using an approximation, A, to said pilot carrier estimation, wherein;

30. A method as claimed in claim 29, wherein K=2.

22. A method as claimed in 20, wherein said multi-carrier transmission system comprises a DMT based VDSL system.