Digital encoding of RF computerized tomography data

• US 6,181,766 B1
• Filed: 08/25/1998
• Issued: 01/30/2001
• Est. Priority Date: 08/25/1998
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Omick, James K., Pearson, Phil E. Jr.
• Primary Examiner(s): Porta, David P.
• Assistant Examiner(s): Dunn, Drew A.
• Application Number:
  US09/139,697
• Time in Patent Office: 889 Days
• Field of Search: 378/15, 378/19, 378/4, 378/98.8, 378/901, 382/131, 382/132, 372/78, 373/39
• US Class Current: 378/15
• CPC Class Codes: A61B 6/56 Details of data transmission or power supply, e.g. use of slip rings
• CPC Class Codes: Y10S 378/901 Computer tomography program or processor

Abstract

A serial digital bit signal having signal bits occurring in a bit interval and at a signal bit speed, and each signal bit representing, alternatively, a first logic state and a second logic state, is transferred across a rotating interface by encoding each first logic state bit with a digital radio frequency (RF) carrier signal and coupling the encoded signal across the interface with an RF slipring.

Claims

1. A computerized tomography system, comprising:

a rotating frame, having an aperture adapted to rotationally encircle a test object placed in an image plane therein, and including an x-ray source and a detector array each disposed on opposite sides of said aperture, said source emitting x-rays within said image plane at each of several angular positions along the rotational path of the aperture and said detector array receiving said emitted x-rays which pass through the test object, said detector array providing a plurality of detectors and adapted for rotation in an image plane coincident with selected axial positions within said aperture, said first frame thereof, said detector array providing an image signal indication of the intensity of the x-rays received thereby, said image signal indication comprising a serial digital bit data signal, each said serial digital bit occurring in an associated bit interval and at a data signal bit speed, and each representing, alternatively, a first logic state and a second logic state which, collectively, are representative of a view of the test object at the related angular position of the aperture;

a stationary frame, in fixed relation to said rotating frame, and including a signal processor with memory for receiving said serial digital bit data signal associated with each said view at each said angular position, for providing a cross-sectional image of the test object as a composite of said views;

a signal transmitter disposed on said rotating frame for encoding said serial digital bit data signal with a digital radio frequency (RF) carrier signal to provide a digitally encoded serial digital bit data signal;

wherein said signal transmitter digitally encodes only the bit intervals associated with each first logic state bit of said serial digital bit data signal;

electromagnetic coupler having first and second elements disposed on said rotating frame and said stationary frame, respectively, said first element receiving said encoded serial digital bit data signal from said signal transmitter for providing electromagnetic coupling thereof to said second element; and

a signal receiver disposed on said second frame and responsive to said second element, for translating said digitally encoded serial digital bit data signal to its pre-encoded state;

wherein said signal receiver translates the received first logic state encoded signal into first logic state bits and second logic state bits in correspondence with the pre-encoded state of said serial digital bit data signal.

2. The system of claim 1, wherein said signal transmitter encodes each said bit interval of each said first logic state bit with a plurality of serial pulses occurring at an RF pulse repetition frequency.

3. The system of claim 2, wherein:

said signal transmitted further including a transmitter clock and a phase locked loop for providing a transparent asynchronous xceiver (transceiver) interface clock signal which is synchronized to said data signal bit speed, and which controls the occurrence of the bit intervals of said digitally encoded serial digital bit data signal to provide synchronization thereof with said data signal bit speed; and

said signal receiver includes signal detection circuitry for recovering said transparent asynchronous xceiver (transceiver) interface signal from the received said digitally encoded serial digital bit data signal, to provide said translation in synchronization with said data signal bit speed.

4. The system of claim 3, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver translates each presence of a majority of said known even number of serial pulses within a bit interval as a first logic state signal bit and translates each other number occurrence of serial pulses as a second logic state signal bit.

5. The system of claim 3, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver detects the presence of each bit interval from said transparent asynchronous xceiver (transceiver) interface clock signal, and counts the occurrence of serial pulses within each detected bit interval, said receiver translating each presence of a majority of said known even number of serial pulses within said detected bit interval as a first logical state signal bit, said receiver translating each other number occurrence of serial pulses as a second logic state signal bit.

6. The system of claim 3, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with four serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver detects the presence of each bit interval from said transparent asynchronous xceiver (transceiver) interface clock signal, and counts the occurrence of serial pulses within each detected bit interval, said receiver translating each presence of three of four and four of four pulses within each detected bit interval as a first logic state signal bit, said receiver translating each presence of no pulses and one of four pulses and three of four pulses within each said detected bit interval as a second logic state signal bit.

7. The system of claim 3, wherein said electromagnetic coupler comprises an RF slipring.

8. The system of claim 7, wherein said signal transmitter provides said four serial pulses at an RF pulse repetition frequency which is at least four times greater than the frequency corresponding to the data signal bit speed.

9. The system of claim 7, wherein said signal transmitter provides said four serial pulses at a substantially fifty percent duty cycle.

10. The system of claim 1, wherein:

said signal transmitter further includes a phase locked loop for providing a transparent asynchronous xceiver (transceiver) interface clock signal which is synchronized to said data signal bit speed, and which controls the occurrence of the bit intervals of said digitally encoded serial digital bit data signal to provide synchronization thereof with said data signal bit speed; and

said signal receiver includes signal detection circuitry for recovering said transparent asynchronous xceiver (transceiver) interface clock signal from the received said digitally encoded serial digital bit data signal, to provide said translation in synchronization with said data signal bit speed.

11. The system of claim 1, wherein said signal transmitter and said signal receiver each comprise emitter coupled logic (ECL) circuit elements.

12. The system of claim 11, wherein said ECL circuit elements are positive ECL (PECL).

13. Apparatus for coupling a serial digital bit signal from a first surface to a second surface which is in relative rotation therewith, the serial digital bit signal comprising signal bits each occurring in an associated bit interval and at a signal bit speed, and each signal bit representing, alternatively, a first logic state and a second logic state, the apparatus comprising:

a signal transmitter disposed on said first surface for encoding said serial digital bit signal with a digital radio frequency (RF) carrier signal to provide a digitally encoded serial digital bit data signal, wherein said signal transmitter digitally encodes only the bit intervals associated with each first logic state bit of said serial digital bit data signal;

electromagnetic coupler having first and second elements disposed on said rotating frame and said stationary frame, respectively, said first element receiving said encoded serial digital bit signal from said signal transmitter for providing electromagnetic coupling thereof to said second element; and

a signal receiver disposed on said second frame and responsive to said second element, for translating said digitally encoded serial digital bit signal to its pre-encoded state, wherein said signal receiver translates the received first logic state encoded signal into first logic state bits and second logic state bits in correspondence with the pre-encoded state of said serial digital bit data signal.

14. The apparatus of claim 13, wherein said signal transmitter encodes each said bit interval of each said first logic state bit with a plurality of serial pulses occurring at an RF pulse repetition frequency.

15. The apparatus of claim 14, wherein

said signal transmitter further including a transmitter clock and a phase locked loop for providing a transparent asynchronous xceiver (transceiver) interface clock signal which is synchronized to said data signal bit speed, and which controls the occurrence of the bit intervals of said digitally encoded serial digital bit data signal to provide synchronization thereof with said data signal bit speed; and

said signal receiver includes signal detection circuitry for recovering said transparent asynchronous xceiver (transceiver) interface clock signal from the received said digitally encoded serial digital bit data signal, to provide said translation in synchronization with said data signal bit speed.

16. The apparatus of claim 15, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver translates each presence of a majority of said known even number of serial pulses within a bit interval as a first logic state signal bit and translates each other number occurrence of serial pulses as a second logic state signal bit.

17. The apparatus of claim 15, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver detects the presence of each bit interval from said transparent asynchronous xceiver (transceiver) interface clock signal, and counts the occurrence of serial pulses within each detected bit interval, said receiver translating each presence of a majority of said known even number of serial pulses within said detected bit interval as a first logic state signal bit, said receiver translating each other number occurrence of serial pulses as a second logic state signal bit.

18. The apparatus of claim 15, wherein:

said signal transmitter encodes each said bit interval of each said first logic state bit with four serial pulses occurring at an RF pulse repetition frequency; and

said signal receiver detects the presence of each bit interval from said transparent asynchronous xceiver (transceiver) interface clock signal, and counts the occurrence of serial pulses within each detected bit interval, said receiver translating each presence of three of four and four of four pulses within said detected bit interval as a first logic state signal bit, said receiver translating each presence of no pulses and one of four pulses and three of four pulses within each said detected bit interval as a second logic state signal bit.

19. The apparatus of claim 18, wherein:

said signal transmitter provides said four serial pulses at an RF pulse repetition frequency which is at least four times greater than the frequency corresponding to the data signal bit speed.

20. The apparatus of claim 18, wherein said signal transmitter provides said four serial pulses at a substantially fifty percent duty cycle.

21. The apparatus of claim 13, wherein:

said signal transmitter further including a transmitter clock and a phase locked loop for providing a transparent asynchronous xceiver (transceiver) interface clock signal which is synchronized to said data signal bit speed, and which controls the occurrence of the bit intervals of said digitally encoded serial digital bit data signal to provide synchronization thereof with said data signal bit speed; and

said signal receiver includes signal detection circuitry for recovering said transparent asynchronous xceiver (transceiver) interface clock signal from the received said digitally encoded serial digital bit data signal, to provide said translation in synchronization with said data signal bit speed.

22. The apparatus of claim 13, wherein said signal transmitter and said signal receiver each comprise emitter coupled logic (ECL) circuit elements.

23. A method of transferring signal data across the rotating interface of a computerized tomography system of the type having a rotating frame mounted in a relatively stationary frame, the rotating frame having an aperture adapted to rotationally encircle a test object placed in an image plane therein for obtaining x-ray views of the test object at one or more angular positions of the rotating frame, each view comprising a serial digital bit data signal, each said serial digital bit occurring in an associated bit interval and at a data signal bit speed, and each representing, alternatively, a first logic state and a second logic state which represent, collectively, the desired view, such serial digital bit data signal associated with each view being provided to a signal processor mounted to the relatively stationary frame, the signal processor providing a cross section image of the test object as a composite of all such views, the method comprising the steps of:

encoding the serial digital bit data signal on the rotating frame by identifying the presence of each bit interval, detecting from among the identified bit intervals those occurring with a first logic state bit, and modulating each such first logic state bit interval with a digital radio frequency (RF) carrier signal to provide a digitally encoded serial digital bit data signal;

using an electromagnetic coupler having first and second elements disposed on the rotating frame and the stationary frame, respectively, and presenting the digitally encoded serial digital bit signal to the first element which provides electromagnetic coupling thereof to the second element; and

receiving the digitally encoded serial digital bit data signal from the second element and translating the encoded signal to its pre-encoded state.

24. The method of claim 23, wherein said step of modulating comprises the step of:

replacing the first logic state signal bit with a plurality of serial pulses occurring at an RF pulse repetition frequency.

25. The method of claim 24, further comprising the steps of:

providing a transparent asynchronous xceiver (transceiver) interface clock signal on the rotating frame;

synchronizing said transparent asynchronous xceiver (transceiver) interface clock signal with the data signal bit speed;

using the synchronized transparent asynchronous xceiver (transceiver) interface clock signal to control the occurrence of the bit intervals of the digitally encoded serial digital bit data signal on the rotating frame, so as to provide synchronization thereof with the data signal bit speed; and

extracting the transparent asynchronous xceiver (transceiver) interface clock signal at the stationary frame from the received digitally encoded serial digital bit data signal, to provide said translation in synchronization with said data signal bit speed.

26. The method of claim 25, wherein:

said step of replacing comprises the step of;

providing said plurality of serial pulses a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said step of translating comprises the steps of;

recording each presence of a majority of said known even number of serial pulses within a bit interval as a first logic state signal bit and recording each other number occurrence of serial pulses as a second logic state signal bit.

27. The method of claim 25, wherein:

said step of replacing comprises the step of;

providing said plurality of serial pulses a known even number of serial pulses occurring at an RF pulse repetition frequency; and

said step of translating comprises the steps of;

detecting the presence of each bit interval as determined from said transparent asynchronous xceiver (transceiver) interface clock signal;

counting the occurrence of serial pulses within each such detected bit interval; and

recording each presence of a majority of said known even number of serial pulses within said detected bit interval as a first logic state signal bit, and recording each other number occurrences of serial pulses as a second logic state signal bit.

28. The method of claim 25, wherein:

said step of replacing comprises the step of;

providing four serial pulses occurring at an RF pulse repetition frequency; and

said step of translating comprises the steps of;

detecting the presence of each bit interval as determined from said taxi clock signal;

recording the occurrence of three of four and four of four pulses within said detected bit interval as a first logic state signal bit, and recording each presence of no pulses and one of four pulses and three of four pulses within said detected bit interval as a second logic state signal bit.