Apparatus for interfacing buses

• US 6,182,180 B1
• Filed: 10/01/1997
• Issued: 01/30/2001
• Est. Priority Date: 05/13/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Nguyen, Ken, Johnson, Karl S., Mahalingam, Mallikarjunan, Liu, Ji-hwan
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US08/942,382
• Time in Patent Office: 1,217 Days
• Field of Search: 395/309, 395/306, 395/308, 395/872, 395/873, 710/129, 710/126, 710/128, 710/52, 710/53, 710/130, 710/110, 710/112, 710/56, 710/57, 710/29, 710/39, 710/48, 710/260, 710/19, 710/74, 710/22, 364/240
• US Class Current: 710/310
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/0787 Storage of error reports, e.g. persistent data storage, storage using memory protection
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A method and apparatus for interfacing buses includes a system interface processor coupled to a first bus and including a command register accessible via a second bus. A request buffer and a response buffer are provided which are accessible via the second bus and coupled to the interface processor. The request buffer can be used to store information to be transmitted from the second bus to the first via the interface processor while the response buffer can be used to store information to be transmitted from the first bus to the second bus via the interface processor. The interface processor may include a status register to indicate the status of the interface controller. The interface controller may also include a command register to receive commands transmitted over the second bus.

Claims

1. A bus interface for controlling the transfer of information between first and second electronic buses, the interface comprising:

a system interface processor coupled to the first bus and having a command register accessible via the second bus and a status register accessible via the second bus for indicating the status of the interface processor;

a request buffer comprising a first in first out memory device accessible via a first address on the second bus and coupled to the interface processor for receiving information from the second bus to be transmitted to the first bus via the interface processor; and

a response buffer comprising a first-in-first-out memory device accessible via said first address on the second bus and coupled to the interface processor.

2. A bus interface according to claim 1, wherein said interface processor is a microcontroller.

3. A bus interface according to claim 1, further including an address decoder coupled to the interface processor, the response buffer and the request buffer, for generating enabling signals for the interface processor, the response buffer and the request buffer in response to address signals and read/write signals from the second bus.

4. A bus interface for controlling the transfer of information between an Inter-IC control bus (I²C bus) and a Industry Standard Architecture (ISA) bus, the interface comprising:

an interface processor coupled to the I²C bus and having a command register accessible through an address via the ISA bus for transmitting commands to the interface processor via the ISA bus;

a request buffer accessible via the ISA bus and coupled to the interface processor for receiving information via the ISA bus to be transmitted to the I²C bus; and

a response buffer accessible via the ISA bus and coupled to the interface processor for receiving information via the I²C bus to be transmitted to the ISA bus.

5. A bus interface according to claim 4, wherein said interface processor further includes a status register accessible via the ISA bus for indicating the status of the interface processor.

6. A bus interface according to claim 4, wherein said interface processor is a microcontroller.

7. A bus interface according to claim 4, wherein said request buffer and said response buffer are first in first out memory devices accessible through a single address on said ISA bus.

8. A bus interface according to claim 4, further including an address decoder coupled to the interface processor, the request buffer and the response buffer, and capable of being coupled to the ISA bus, the address decoder generating enabling signals for the interface processor, the request buffer and the response buffer in response to address signals and read/write signals from the ISA bus.

9. A bus interface for controlling the transfer of information between first and second electronic buses, the interface comprising:

interface processor means for regulating the transfer of information between the first and second buses, the interface processor capable of being coupled to the first bus having a command register means for receiving commands via the second bus and having a status register means accessible via the second bus for indicating the status of said interface processor means;

a request buffer means accessible via the second bus and coupled to the interface processor for receiving information via the second bus which is to be transmitted via the first bus; and

a response buffer means accessible via the second bus and coupled to the interface processor for receiving information from the bus via the interface processor means which is to be transmitted via the second bus;

wherein the request buffer means and the response buffer means are first-in-first-out memory devices, both accessible through a single address on the second bus.

10. A bus interface according to claim 9, wherein said interface processor means is a microcontroller.

11. A bus interface according to claim 9, further including an address decoder means coupled to the interface processor means, the response buffer means and the request buffer means, for generating enabling signals for the interface processor means, the response buffer means and the request buffer means in response to address signals and read/write signals from the second bus.

12. A bus interface according to claim 9, further including a driver means, capable of communicating with said interface processor means over the second bus, for writing messages to the request buffer means, writing commands to the command register means and reading the status register means.

13. A bus interface for controlling the transfer of information between an Inter-IC control bus (I²C bus) and an Industry Standard Architecture (ISA) bus, the interface comprising:

an interface processor coupled to the I²C bus and having a command register accessible via the ISA bus for transmitting commands to the interface processor via the ISA bus;

a status register accessible via the ISA bus for indicating the status of the interface processor;

a request buffer accessible via the ISA bus and coupled to the interface processor for receiving information via the ISA bus to be transmitted to the I²C bus;

a response buffer accessible via the ISA bus and coupled to the interface processor for receiving information via the I²C bus to be transmitted to the ISA bus;

an address decoder coupled to the interface processor, the request buffer and the response buffer, and capable of being coupled to the ISA bus, the address decoder generating enabling signals for the interface processor, the request buffer and the response buffer in response to address signals and read/write signals from the ISA bus; and

a software driver means for receiving client messages to be transferred across the interface, reviewing the status register, writing the client messages to the request buffer, and writing commands to the command register.