Method of operating a memory device having a variable data input length

• US 6,182,184 B1
• Filed: 02/22/2000
• Issued: 01/30/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/510,213
• Time in Patent Office: 343 Days
• Field of Search: 710/129, 710/100, 710/35, 365/233, 365/235, 365/238.5
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of controlling a memory device. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. A first portion of the first amount of data is provided to the memory device synchronously with respect to a first transition of an external clock signal. A second portion of the first amount of data is provided to the memory device synchronously with respect to a second transition of the external clock signal. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Claims

1. A method of controlling a memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be sampled by the memory device in response to a write request;

issuing a first write request to the memory device, wherein in response to the first write request the memory device inputs the first amount of data corresponding to the first block size information; and

providing a first portion of the first amount of data to the memory device synchronously with respect to a first transition of an external clock signal, and a second portion of the first amount of data synchronously with respect to a second transition of the external clock signal.

2. The method of claim 1 further including providing a second block size information to the memory device wherein the second block size information defines a second amount of data to be input by the memory device in response to a second write request.

3. The method of claim 1 further including:

issuing a second write request to the memory device, wherein in response to the second write request the memory device samples a second amount of data corresponding to second block size information; and

providing a first portion of the second amount of data to the memory device synchronously with respect to a third transition of the external clock signal, and a second portion of the second amount of data synchronously with respect to a fourth transition of the external clock signal.

4. The method of claim 1 further including:

issuing a request for a read operation to the memory device, wherein in response to the request for a read operation, the memory device outputs a second amount of data corresponding to second block size information; and

receiving the second amount of data from the memory device.

5. The method of claim 1 wherein the first block size information and the first write request are included in a request packet.

6. The method of claim 5 wherein the first block size information and the first write request are included in the same request packet.

7. The method of claim 1 wherein the data is provided to the memory device after a number of clock cycles of the external clock signal transpires.

8. The method of claim 7 wherein the number of clock cycles is represented by a fraction.

9. The method of claim 1 wherein the first block size information is a binary representation of the first amount of data to be sampled in response to the first write request.

10. The method of claim 1 wherein the first amount of data corresponding to the first block size information is provided synchronously during a plurality of clock cycles of the external clock signal.

11. The method of claim 1 wherein the first transition of the external clock signal is a rising edge transition and the second transition of the external clock signal is a falling edge transition.

12. The method of claim 1 wherein the first and second transitions of the external clock signal transpire during a common clock cycle of the external clock signal.

13. A method of operation of a memory device, wherein the memory device includes a plurality of memory cells, the method of operation of the memory device comprises:

receiving first block size information from a master, wherein the first block size information defines a first amount of data to be sampled by the memory device in response to a write request;

receiving a first write request from the master; and

sampling a first portion of the first amount of data synchronously with respect to a first transition of an external clock signal and a second portion of the first amount of data synchronously with respect to a second transition of the external clock signal.

14. The method of claim 13 wherein the first transition of the external clock signal is a rising edge transition and the second transition of the external clock signal is a falling edge transition.

15. The method of claim 13 further including receiving second block size information from the master, wherein the second block size information defines a second amount of data to be input by the memory device in response to a second write request.

16. The method of claim 13 further including:

receiving a second write request from the master; and

inputting a second amount of data corresponding to second block size information synchronously with respect to a third transition of the external clock signal and a second portion of the first amount of data synchronously with respect to a fourth transition of the external clock signal.

17. The method of claim 16 wherein the third and fourth transitions of the external clock cycle transpire during a common clock cycle of the external clock signal.

18. The method of claim 13 wherein the first block size information and the first write request are included in the same request packet.

19. The method of claim 13 wherein the first block size information is a binary representation of the first amount of data to be input in response to the first write request.

20. The method of claim 13 wherein the first amount of data corresponding to the first block size information is input synchronously during the same clock cycle of the external clock signal.

21. The method of claim 13 wherein the first amount of data corresponding to the first block size information is sampled synchronously during a plurality of clock cycles of the external clock signal.

22. The method of claim 13 further including generating an internal clock signal using a delay locked loop circuit and the external clock signal wherein the first amount of data corresponding to the first block size information is sampled in response to the internal clock signal.

23. The method of claim 13 further including generating first and second internal clock signals using clock generation circuitry and the external clock signal wherein the first amount of data corresponding to the first block size information is sampled synchronously with respect to the first and second internal clock signals.

24. A method of operation of an integrated circuit device having a synchronous interface, the method of operation of the integrated circuit device comprising:

receiving block size information, wherein the block size information defines an amount of data to be sampled by the integrated circuit device in response to a write request;

receiving a write request; and

sampling a first portion of the amount of data synchronously with respect to a first transition of an external clock signal and a second portion of the amount of data synchronously with respect to a second transition of the external clock signal, wherein the first and second transitions of the external clock signal occur during the same clock cycle of the external clock signal.

25. The method of claim 24 wherein the first transition of the external clock signal is a rising edge transition and the second transition of the external clock signal is a falling edge transition.

26. The method of claim 24 further including:

receiving a read request; and

outputting a first portion of the amount of data synchronously with respect to a third transition of the external clock signal and a second portion of the amount of data synchronously with respect to a fourth transition of the external clock signal.

27. The method of claim 24 wherein the block size information and the write request are included in the same request packet.

28. The method of claim 24 wherein the block size information is a binary representation of the amount of data to be sampled in response to the write request.

29. The method of claim 24 further including generating an internal clock signal using a delay locked loop and the external clock signal wherein the amount of data corresponding to the block size information is input synchronously with respect to the internal clock signal.