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Method and tool for computer bus fault isolation and recovery design verification

  • US 6,182,248 B1
  • Filed: 04/07/1998
  • Issued: 01/30/2001
  • Est. Priority Date: 04/07/1998
  • Status: Expired due to Fees
First Claim
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1. A method of verifying error detection and recovery designs, comprising:

  • connecting an error injection tool to a selected bus conductor within a bus;

    monitoring the bus for a predetermined transaction or cycle when a selected device is driving the bus;

    responsive to detecting the predetermined transaction or cycle on the bus, overdriving the selected bus conductor to a logic high or a logic low to inject an error on the bus for one cycle;

    monitoring a response of the bus to the injected error; and

    responsive to determining that an error was not infected onto the bus, repeating the steps of monitoring the bus for a predetermined transaction or cycle when a selected device is driving the bus, responsive to detecting the predetermined transaction or cycle on the bus, overdriving the selected bus conductor to a logic high or a logic low to inject an error on the bus, and monitoring a response of the bus to the injected error, until an error is successfully injected onto the bus.

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