Method and device for fast and accurate parasitic extraction

• US 6,182,269 B1
• Filed: 08/06/1997
• Issued: 01/30/2001
• Est. Priority Date: 08/06/1997
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Laubhan, Richard A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): JONES, HUGH M
• Application Number:
  US08/907,183
• Time in Patent Office: 1,273 Days
• Field of Search: 395/500.06, 395/500.07, 395/500.13, 716/12, 716/5, 716/6
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method designates nets of a circuit for detailed parasitic impedance extraction (e.g., calculation of parasitic resistance and/or capacitance components of circuit interconnects) by comparing an estimated net impedance parameter with other circuit characteristics, such as the output resistance of a driver cell or the gate capacitance provided by load elements connected to the net. One or more threshold percentage parameters may be used in the comparison. Also, based on the designation, the estimated net impedance parameter or the detailed parasitic impedance value may be used for calculating logic delay through a logic cell driving the net. A program stored on a computer readable medium also operates to evaluate the parasitic impedance of circuit interconnects relative to other circuit characteristics and, depending on this evaluation, calculates the logic delay of a logic cell driving the net using an estimated net impedance parameter or detailed parasitic impedance parameter.

Claims

1. A computer-readable medium that stores a computer executable program for extracting a parasitic impedance parameter associated with a net wherein the computer executable program comprises:

a module for determining net length that receives as inputs a net from a layout database and that generates as outputs a port-to-port net length and a total net length;

a module for estimating net resistance that receives as inputs the port-to-port net length from the module for determining net length and a resistance per unit length from a technology database and that generates as output an estimated net resistance;

a module for determining output resistance that receives as inputs a driving cell from a netlist and a large-signal output impedance of the driving cell from a cell library and that generates as output an output resistance equal to the large-signal output impedance of the driving cell;

a module for determining whether to designate the net for detailed parasitic extraction that receives as inputs the output resistance from the module for determining output resistance, a first threshold resistance percentage from the technology database, a second threshold resistance percentage from the technology database, the estimated net resistance from the module for estimating net resistance, a gate capacitance, an estimated net capacitance, a first threshold capacitance percentage from the technology database, and a second threshold capacitance percentage from the technology database and that performs one of the following;

designates the net for parasitic extraction if the estimated net resistance is greater than the product of the output resistance times the first threshold resistance percentage or if the estimated net capacitance is greater than the product of the gate capacitance times the first threshold capacitance percentage;

generates as output parasitic results equal to the estimated net resistance and the estimated net capacitance if the estimated net resistance is greater than the product of the output resistance times the second threshold resistance percentage or if the estimated net capacitance is greater than the product of the gate capacitance times the second threshold capacitance percentage; and

generates as output parasitic results equal to zero if the estimated net resistance is not greater than the product of the output resistance times the

second threshold resistance percentage and if the estimated net capacitance is not greater than the product of the gate capacitance times the second threshold capacitance percentage;

a module for performing parasitic extraction coupled to the module for determining whether to designate the net for detailed parasitic extraction that uses a distributed impedance model to generate as output parasitic results;

a module for estimating net capacitance that receives as inputs the total net length from the module for determining net length and a capacitance per unit length from the technology database and that generates as output the estimated net capacitance;

a module for determining gate capacitance that receives as inputs a plurality of load cells from the netlist and load capacitances of the plurality of load cells from the cell library and that calculates the sum of the load capacitances to generate as output the gate capacitance; and

a module for determining chip level delay that receives as inputs the parasitic results from the module for performing parasitic extraction and the parasitic results from the module for determining whether to designate the net for detailed parasitic extraction and that generates as output a chip level delay of the driver cell.