Testing method and apparatus assuring semiconductor device quality and reliability

• US 6,184,048 B1
• Filed: 11/03/1999
• Issued: 02/06/2001
• Est. Priority Date: 11/03/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ramon, Joseph
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/433,174
• Time in Patent Office: 461 Days
• Field of Search: 438/14, 438/17, 438/18, 438/19, 438/5, 438/10, 364/468, 364/17, 324/522, 371/28
• US Class Current: 438/14
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22

Abstract

A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising first, electrically testing the devices outside their specified operating voltage range, yet within the capabilities of the structures produced by the process steps, thereby generating raw electrical test data; second, comparing the test data to values expected from the design of the devices, thereby providing non-electrical characterization of the devices to verify compositional and structural features; and third, correlating the features with the documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices. After eliminating the outlier devices, the accepted devices do no longer have to undergo the traditional burn-in process.

Claims

1. A method for assuring quality and reliability of semiconductor integrated circuit devices, fabricated by a series of documented process steps, comprising:

electrically testing said devices outside their specified operating voltage range, yet within the capabilities of the structures produced by said process steps, thereby generating raw electrical test data;

comparing said test data to values expected from the design of said devices, thereby providing non-electrical characterization of said devices to verify compositional and structural features; and

correlating said features with said documented process steps to find deviations therefrom, as well as structural defects, thereby identifying outlier devices.

2. The method according to claim 1 wherein said testing comprises:

inputting test voltages higher than specification at input terminals selected on circuit design;

measuring quiescent leakage current; and

correlating said leakage current with pre-defined limits, thereby finding devices with leakage current higher than the pre-defined limits as reason for rejection.

3. The method according to claim 2 further comprising the steps of stressing said devices and repeating the measurement of said leakage current, thereby detecting any difference between first and second leakage, causing said devices to be rejected.

4. The method according to claim 2 further comprising the step of repeating the measurement of said leakage current at different logic state of said devices, thereby detecting any difference between first and second leakage, causing said devices to undergo distribution testing and potential rejection.

5. The method according to claim 1 wherein said testing comprises:

inputting test voltages lower than specification at input terminals selected on circuit design;

measuring quiescent leakage current; and

correlating said leakage current with pre-defined limits, thereby finding devices with leakage current higher than the pre-defined limits as reason for rejection.

6. The method according to claim 1 wherein said testing comprises:

inputting test voltages in a voltage range at least as great as the specified input voltage range at input terminals selected on circuit design;

measuring output voltages at selected output terminals to determine state of said circuit at output.

7. The method according to claim 6 wherein said voltage range is determined by said capabilities of said process steps used for fabricating said semiconductor devices.

8. The method according to claim 6 wherein said voltage range includes higher as well as lower voltages than defined by device specification.

9. The method according to claim 1 wherein said testing comprises:

inputting a high test voltage, the high test voltage near the device'"'"'s specified maximum input voltage and measuring quiescent leakage current;

inputting a low test voltage, the low test voltage near the device'"'"'s specified minimum input voltage and measuring quiescent leakage current; and

interpolating the data for determining a linear relation as reason for rejection.

10. The method according to claim 1 wherein said testing comprises:

measuring input leakage current;

correlating said leakage current with pre-defined limits set lower than specification, thereby finding devices with leakage current higher than pre-defined limits as reason for rejection.

11. The method according to claim 1 wherein said testing comprises:

measuring electrical parameters related to process parameters having low Cpk;

correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.

12. The method according to claim 1 wherein said electrical testing is performed at ambient temperature.

13. The method according to claim 1 wherein said testing eliminates the need for burn-in of all said circuits which pass said testing and correlating.

14. The method according to claim 1 wherein said testing results in devices having a voltage margin of ±

25%.

15. The method according to claim 1 wherein said electrical testing excludes functional tests at the device'"'"'s rated operating speed.

16. The method according to claim 1 wherein said electrical testing excludes functional tests at 400 megahertz.

17. The method according to claim 1 wherein said testing comprises:

measuring electrical parameters related to process parameters having Cpk below about 1.5;

correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.

18. The method according to claim 1 wherein said testing comprises:

measuring electrical parameters related to process parameters having Cpk below 2;

correlating said electrical parameters with pre-defined limits, thereby finding outlier devices with potential for rejection.