CMOS image sensor with equivalent potential diode and method for fabricating the same

• US 6,184,055 B1
• Filed: 02/26/1999
• Issued: 02/06/2001
• Est. Priority Date: 02/28/1998
• Status: Expired due to Term

• Current Assignee: Photonic Imaging Solutions Inc. (Quest Patent Research Corporation)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Nan Yi, Lee, Ju Il, Yang, Woodward
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/258,814
• Time in Patent Office: 711 Days
• Field of Search: 438/48, 438/57, 252/92, 252/33
• US Class Current: 438/57
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70

Abstract

A CMOS image sensor according to the present invention has a low-voltage photodiode which is fully depleted at a bias of 1.2-4.5V. The photodiode comprises: a P-epi layer; a field oxide layer dividing the P-epi layer into a field region and an active region; a N⁻ region formed within the P-epi layer, wherein the first impurity region is apart from the isolation layer; and a P⁰ region of the conductive type formed beneath a surface of the P-epi layer and on the N⁻ region, wherein a width of the P⁰ region is wider than that of the N⁻ region so that a portion of the P⁰ region is formed on the P-epi layer, whereby the P⁰ region has the same potential as the P-epi layer.

Claims

1. A method for fabricating a photodiode used in a CMOS image sensing device, comprising the steps of:

providing a semiconductor layer of a first conductive type;

forming an isolation layer dividing the semiconductor layer into a field region and an active region;

forming a first impurity region of a second conductive type within the semiconductor layer using a first ion implantation mask, wherein the first ion implantation mask covers a portion of the semiconductor layer so that the first impurity region is apart from the isolation layer; and

forming a second impurity region of the first conductive type beneath a surface of the semiconductor layer and on the first impurity region using a second ion implantation mask, wherein the second ion implantation mask opens a portion of the semiconductor layer so that a width of the second impurity region is wider than that of the first impurity region and a portion of the second impurity region is in contact with the semiconductor layer.

2. The method in accordance with claim 1, wherein an impurity concentration of the first impurity region is higher than that of the semiconductor layer and an impurity concentration of the second impurity region is higher than that of the first impurity region.

3. The method in accordance with claim 1, wherein the semiconductor layer is an epitaxial layer grown on a semiconductor substrate of the first conductive type.

4. A method for fabricating a CMOS image sensing device having a photodiode, the method comprising the steps of:

providing a semiconductor layer of a first conductive type;

forming an isolation layer on the semiconductor layer in order to define a field region and an active region;

forming a gate electrode of a depletion transistor on the semiconductor layer, being apart from the isolation layer;

forming a first ion implantation mask exposing a portion of a light sensing area which is positioned between the isolation layer and the gate electrode of the depletion transistor, wherein the first ion implantation mask covers the isolation layer and a portion of the light sensing area which is near to the isolation layer;

forming a first impurity region, by introducing impurity ions of a second conductive type into the exposed light sensing area;

removing the first ion implantation mask;

forming a second ion implantation mask opening all the light sensing area, wherein the second ion implantation mask is positioned at an interface between the isolation layer and the light sensing area so that an open area of the second ion implantation mask is wider than that of the first ion implantation; and

forming a second impurity region, by introducing impurity ions of the first conductive type into all the light sensing area,

whereby the first impurity region is apart from the isolation layer, a width of the second impurity region is wider than that of the first impurity region, and a portion of the second impurity region is in contact with the semiconductor layer.

5. The method in accordance with claim 4, wherein the gate electrode of the depletion transistor has such a thickness as to block the impurity ions so that the impurity ions are not introduced into the semiconductor layer beneath the gate electrode.

6. The method in accordance with claim 5, wherein an edge of the first ion implantation mask is formed on the gate electrode so that the first impurity region is self-aligned with the gate electrode.

7. The method in accordance with claim 5, wherein an edge of the second ion implantation mask is formed on the gate electrode of the depletion transistor so that the second impurity region is self-aligned with the gate electrode.

8. The method in accordance with claim 5, wherein the gate electrode of the depletion transistor comprises a polysilicon layer and a silicide layer formed on the polysilicon layer.

9. The method in accordance with claim 8, wherein the polysilicon layer and the silicide layer have a thickness of above 2000 Å

and above 1500 Å

, respectively.

10. The method in accordance with claim 4, wherein the semiconductor layer is an epitaxial layer grown on a semiconductor substrate of the first conductive type.

11. The method in accordance with claim 10, wherein an impurity concentration of the semiconductor substrate is higher than that of the semiconductor layer.

12. A method for fabricating a CMOS image sensing device having a photodiode, the method comprising:

a first step of providing a semiconductor layer of a first conductive type;

a second step of forming a well region of the first conductive type in a portion of the semiconductor layer;

a third step of introducing impurity ions into the well region in order to adjust a threshold voltage;

a forth step of forming a first gate for a transfer transistor, a second gate for a reset transistor and at least one third gate for an output transistor, wherein the first gate and the second gate are formed outside of the well region and the third gate is formed on the well region and wherein a common active region of the reset transistor and the output transistor is positioned at a boundary between the semiconductor layer and the well region;

a fifth step of forming a photodiode in the semiconductor layer, wherein the photodiode electrically coupled to the transfer transistor;

a sixth step of forming a first ion implantation mask exposing the well region and introducing low concentration impurity ions of a second conductive type into the well region;

a seventh step of forming an insulating spacer layer a sidewall of the third gate; and

an eight step of forming a second ion implantation mask exposing the semiconductor layer and the well region, except for the photodiode, and introducing high concentration impurity ions of the second conductive type into the semiconductor layer and the well region,

whereby the transfer and reset transistors, whose active regions are formed in the semiconductor layer, operate in a depletion mode, and the output transistor, whose an active region is formed in the well region, operates in an enhancement mode.

13. The method in accordance with claim 12, wherein the semiconductor layer is an epitaxial layer formed on a semiconductor substrate of the first conductive type and wherein a concentration of the semiconductor substrate is higher than that of the semiconductor layer.

14. The method in accordance with claim 13, wherein the semiconductor layer is formed to a thickness of approximately 2 to 5 μ

m.

15. The method in accordance with claim 12, wherein the third gate comprises:

a fourth gate for a drive transistor of the CMOS image sensor; and

a fifth gate for a select transistor of the CMOS image sensor, wherein the drive and select transistors are formed in the well region and have a common source/drain region.

16. The method in accordance with claim 12, wherein the third step comprises the steps of:

forming a third ion implantation mask exposing the well region;

introducing ions into the well region for adjusting a threshold voltage of the output transistor; and

introducing ions into the well region for adjusting a punchthrough of the output transistor.

17. The method in accordance with claim 12, wherein the fourth step of comprises the steps of:

forming a first impurity region of the second conductive type into the semiconductor layer so that the first impurity region is surrounded by the semiconductor layer; and

forming a second impurity region into the semiconductor layer and over the first impurity region, wherein the second impurity region is in contact with the semiconductor layer at a side of the first impurity region.

18. The method in accordance with claim 17, wherein an impurity concentration of the first impurity region is higher than that of the semiconductor layer and an impurity concentration of the second impurity region is higher than that of the first impurity region.

19. The method in accordance with claim 18, wherein the photodiode has a full depletion layer in the semiconductor layer at approximately 1.2-4.5V.

20. The method in accordance with claim 12, wherein the first conductive type is a P-type and the second conductive type is an N-type.

21. The method in accordance with claim 12, wherein the method further comprises the steps of:

forming a plurality of metal layers isolated from adjacent metal layers by an insulating layer;

forming a passivation layer on the resulting structure; and

forming a color filter on the passivation layer.