Process for forming a high-K gate dielectric

• US 6,184,072 B1
• Filed: 05/17/2000
• Issued: 02/06/2001
• Est. Priority Date: 05/17/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Adetutu, Olubunmi O., Nguyen, Bich-Yen, Hobbs, Christopher C., Kaushik, Vidya S.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/571,588
• Time in Patent Office: 265 Days
• Field of Search: 438/785, 438/786, 438/787, 438/197, 438/287, 438/299, 438/301, 438/585, 438/656
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO₂ or a combination of SiO₂, SiO₃ and SiO₄ (oxide-nitride or oxynitride) stacks.

Claims

1. A method of forming a transistor on a substrate having a semiconductor surface, comprising the steps of:

implanting a metal into the first portion of the surface;

applying oxygen to the first portion of the surface to grow an oxide of the metal and the semiconductor surface;

forming a gate conductor over the first portion of the surface; and

forming a source and drain in the semiconductor surface adjacent to the gate to leave a channel between the source and drain and under the gate conductor.

2. The method of claim 1, wherein the semiconductor surface is silicon and the metal is selected from hafnium and zirconium.