Method to fabricate the MOS gate

• US 6,184,116 B1
• Filed: 01/11/2000
• Issued: 02/06/2001
• Est. Priority Date: 01/11/2000
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Kwan-Hwa, Shen, Yun-Hung, Lin, Yu-Lun
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/480,264
• Time in Patent Office: 392 Days
• Field of Search: 438/197, 438/199, 438/279, 438/283, 438/587, 438/585, 438/275
• US Class Current: 438/587
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions

Abstract

A new method for forming a feature, such as a gate electrode, having a feature size, or a line width, controlled by spacer width and not limited by photolithographic resolution is described. A dielectric stack is provided on the surface of a semiconductor substrate. The dielectric stack is etched away where it is not covered by a mask wherein the remaining dielectric stack has a width equal to the spacing between two of gate electrodes to be formed. A gate oxide layer is grown on the surface of the semiconductor substrate not covered by the dielectric stack. A polysilicon layer is deposited overlying the gate oxide layer and the dielectric stack. The polysilicon layer is etched back to leave spacers on the sidewalls of the dielectric stack. A dielectric layer is deposited overlying the substrate and polished back whereby an upper portion of the dielectric stack and the spacers are polished away. The remaining dielectric layer and the dielectric stack ar removed whereby the spacers remain forming narrow gate electrodes having the gate oxide layer thereunder to complete fabrication of gate electrodes in the manufacture of an integrated circuit device. This process can be integrated with a conventional lithographic process for forming wide gate electrodes as well.

Claims

1. A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising:

providing a dielectric stack on the surface of a semiconductor substrate;

etching away said dielectric stack where it is not covered by a mask wherein remaining said dielectric stack has a width equal to the spacing between two of planned said gate electrodes;

growing a gate oxide layer on the surface of said semiconductor substrate not covered by said dielectric stack;

depositing a polysilicon layer overlying said gate oxide layer and said dielectric stack;

etching back said polysilicon layer to leave spacers on the sidewalls of said dielectric stack;

depositing a dielectric layer overlying said dielectric stack and said spacers;

polishing back said dielectric layer whereby upper portions of said dielectric stack and said spacers are polished away; and

removing remaining said dielectric layer and said dielectric stack whereby said spacers remain forming said gate electrodes having said gate oxide layer thereunder to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.

2. The method according to claim 1 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxide on the surface of said semiconductor substrate;

depositing a layer of silicon nitride overlying said silicon oxide layer; and

depositing a layer of tetraethoxysilane (TEOS) oxide overlying said silicon nitride layer.

3. The method according to claim 1 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxynitride on the surface of said semiconductor substrate;

depositing a layer of silicon nitride overlying said silicon oxynitride layer; and

depositing a layer of tetraethoxysilane (TEOS) oxide overlying said silicon nitride layer.

4. The method according to claim 1 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxide on the surface of said semiconductor substrate; and

depositing a layer of borophospho-TEOS oxide overlying said silicon oxide layer.

5. The method according to claim 1 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxynitride on the surface of said semiconductor substrate; and

depositing a layer of borophospho-TEOS oxide overlying said silicon oxynitride layer.

6. The method according to claim 1 wherein said gate oxide layer has a thickness of between about 10 and 50 Angstroms.

7. The method according to claim 1 wherein said polysilicon layer has a thickness of between about 700 and 3000 Angstroms.

8. The method according to claim 1 wherein said dielectric layer comprises TEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

9. The method according to claim 1 wherein said dielectric layer comprises BPTEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

10. The method according to claim 1 wherein said gate electrodes have a width of between about 500 and 2500 Angstroms.

11. The method according to claim 1 wherein said gate electrodes have a width as small as about 300 Angstroms.

12. A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising:

depositing a layer of silicon oxide on the surface of a semiconductor substrate;

depositing a layer of silicon nitride overlying said silicon oxide layer;

depositing a layer of tetraethoxysilane (TEOS) oxide overlying said silicon nitride layer;

etching away said TEOS oxide layer, said silicon nitride layer, and said silicon oxide layer where they are not covered by a mask to leave a dielectric stack wherein said dielectric stack has a width equal to the spacing between two of planned said gate electrodes;

growing a gate oxide layer on the surface of said semiconductor substrate not covered by said dielectric stack;

depositing a polysilicon layer overlying said gate oxide layer and said dielectric stack;

etching back said polysilicon layer to leave spacers on the sidewalls of said dielectric stack;

depositing a dielectric layer overlying said dielectric stack and said spacers;

polishing back said dielectric layer whereby an upper portion of said dielectric stack and said spacers are polished away; and

removing remaining said dielectric layer and said dielectric stack whereby said spacers remain forming said gate electrodes having said gate oxide layer thereunder to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.

13. The method according to claim 12 wherein said silicon oxide layer has a thickness of between about 50 and 150 Angstroms.

14. The method according to claim 12 wherein said silicon nitride layer has a thickness of between about 200 and 500 Angstroms.

15. The method according to claim 12 wherein said TEOS oxide layer has a thickness of between about 2000 and 3000 Angstroms.

16. The method according to claim 12 wherein said gate oxide layer has a thickness of between about 10 and 50 Angstroms.

17. The method according to claim 12 wherein said polysilicon layer has a thickness of between about 700 and 3000 Angstroms.

18. The method according to claim 12 wherein said dielectric layer comprises TEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

19. The method according to claim 12 wherein said gate electrodes have a width of between about 500 and 2500 Angstroms.

20. The method according to claim 12 wherein said gate electrodes have a width as small as about 300 Angstroms.

21. A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising:

providing a dielectric stack on the surface of a semiconductor substrate;

etching away said dielectric stack where it is not covered by a mask wherein remaining said dielectric stack has a width equal to the spacing between two of planned said gate electrodes;

growing a gate oxide layer on the surface of said semiconductor substrate not covered by said dielectric stack;

depositing a polysilicon layer overlying said gate oxide layer and said dielectric stack;

etching back said polysilicon layer to leave spacers on the sidewalls of said dielectric stack wherein said spacers have a width as small as between 300 and 800 Angstroms;

depositing a dielectric layer overlying said dielectric stack and said spacers;

polishing back said dielectric layer whereby upper portions of said dielectric stack and said spacers are polished away wherein said upper portions comprise ⅓

of said dielectric stack; and

removing remaining said dielectric layer and said dielectric stack whereby said spacers remain forming said gate electrodes having said gate oxide layer thereunder to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.

22. The method according to claim 21 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxide on the surface of said semiconductor substrate;

depositing a layer of silicon nitride overlying said silicon oxide layer; and

depositing a layer of tetraethoxysilane (TEOS) oxide overlying said silicon nitride layer.

23. The method according to claim 21 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxynitride on the surface of said semiconductor substrate; and

depositing a layer of borophospho-TEOS oxide overlying said silicon oxynitride layer.

24. The method according to claim 21 wherein said gate oxide layer has a thickness of between about 10 and 50 Angstroms.

25. The method according to claim 22 wherein said dielectric layer comprises TEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

26. The method according to claim 23 wherein said dielectric layer comprises BPTEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

27. A method of integrating the fabrication of both narrow and wide gate electrodes in the manufacture of an integrated circuit device comprising:

providing a dielectric stack on the surface of a semiconductor substrate;

etching away said dielectric stack where it is not covered by a mask wherein remaining said dielectric stack has a width equal to the spacing between two of planned said narrow gate electrodes;

growing a gate oxide layer on the surface of said semiconductor substrate not covered by said dielectric stack;

depositing a polysilicon layer overlying said gate oxide layer and said dielectric stack;

forming a first mask over said polysilicon layer where said wide gate electrodes are to be formed;

etching back said polysilicon layer not covered by said first mask to leave spacers on the sidewalls of said dielectric stack;

thereafter removing said first mask;

depositing a dielectric layer overlying said substrate;

thereafter polishing back said dielectric layer whereby upper portions of said dielectric stack and said spacers are polished away wherein said upper portions comprise about ⅓

of said dielectric stack;

removing remaining said dielectric layer and said dielectric stack whereby said spacers remain forming said narrow gate electrodes having said gate oxide layer thereunder;

forming a second mask covering said narrow gate electrodes and forming a pattern over said polysilicon layer for forming said wide gate electrodes;

patterning said polysilicon layer not covered by said second mask to form said wide gate electrodes to complete integration of said fabrication of both narrow and wide gate electrodes in the manufacture of said integrated circuit device.

28. The method according to claim 27 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxide on the surface of said semiconductor substrate;

depositing a layer of silicon nitride overlying said silicon oxide layer; and

depositing a layer of tetraethoxysilane (TEOS) oxide overlying said silicon nitride layer.

29. The method according to claim 27 wherein said step of providing said dielectric stack comprises:

depositing a layer of silicon oxynitride on the surface of said semiconductor substrate; and

depositing a layer of borophospho-TEOS oxide overlying said silicon oxynitride layer.

30. The method according to claim 27 wherein said gate oxide layer has a thickness of between about 10 and 50 Angstroms.

31. The method according to claim 27 wherein said polysilicon layer has a thickness of between about 700 and 3000 Angstroms.

32. The method according to claim 27 wherein said dielectric layer comprises TEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

33. The method according to claim 27 wherein said dielectric layer comprises BPTEOS oxide deposited to a thickness of between about 2000 and 3000 Angstroms.

34. The method according to claim 27 wherein said narrow gate electrodes have a width as small as between about 300 and 800 Angstroms.