Integrated circuit package for flip chip

• US 6,184,463 B1
• Filed: 04/13/1998
• Issued: 02/06/2001
• Est. Priority Date: 04/13/1998
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Panchou, Karen A., Newton, Charles M.
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): WALKENHORST, DAVID W
• Application Number:
  US09/059,080
• Time in Patent Office: 1,030 Days
• Field of Search: 174/52.2, 174/52.3, 174/52.4, 257/693, 257/723, 257/724, 257/778
• US Class Current: 174/558
• CPC Class Codes: H01L 22/00 Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An integrated circuit package includes a ceramic substrate having a cut out configured to receive a flip chip. The cut out includes vias formed as through holes. A flip chip is received within the cut out of the ceramic substrate and has conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip. The conductive bumps are received within the through holes of the ceramic substrate. A second integrated circuit chip is mounted on the flip chip in back-to-back relationship. A controlled impedance line is secured to the conductive bumps and acts as a coax. In another aspect of the present invention, a heat sink can be mounted on the back of the flip chip, and the second integrated circuit chip mounted on the heat sink.

Claims

1. An integrated circuit package comprising:

a ceramic substrate having opposing upper and lower sides and formed from a plurality of stacked ceramic layers having a cut out configured to receive a flip chip, said cut out including through holes extending through to the lower side of said ceramic substrate, wherein one of said stacked ceramic layers includes a metallized conductive pattern forming a grounding signal path located substantially medially within the ceramic substrate;

a gallium arsenide integrated circuit flip chip received within the cut out of the ceramic substrate and having conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip, wherein the conductive bumps extend downward and are received within the through holes of the ceramic substrate;

a controlled impedance line secured to the conductive bumps;

a second integrated circuit chip mounted back-to-back on the flip chip received within the cut out, a conductive epoxy positioned between the flip chip and second integrated circuit chip and securing said chips to each other, wherein said conductive epoxy is connected to said grounding signal path for back-to-back grounding of said flip chip and second integrated circuit chip, said second integrated circuit chip including electrical contacts that are upward in direction; and

a conductive pattern positioned on said upper side of said ceramic substrate and connected to said electrical contacts on said second integrated circuit chip.

2. A package according to claim 1, wherein said conductive bumps are formed from gold.

3. A package according to claim 1, and further comprising a conductive ink plated on the through holes.

4. A package according to claim 1, and further comprising a means for adhesively securing said controlled impedance line to the conductive bumps.

5. A package according to claim 1, and further comprising a second stepped cut out for receiving the second integrated circuit chip.

6. A package according to claim 1, wherein said conductive bumps are formed of epoxy having a conductive material impregnated therein.

7. An integrated circuit package comprising:

a ceramic substrate having opposing upper and lower sides and formed from a plurality of stacked ceramic layers and having conductive patterns formed on the upper side thereon, and a cut out configured to receive a flip chip, said cut out including through holes extending through to the lower side of said ceramic substrate, and a metallized conductive pattern located substantially medially within the ceramic substrate and on one of said stacked ceramic layers and forming a grounding signal path

a gallium arsenide integrated circuit flip chip received within the cut out of the ceramic substrate and having conductive bumps formed thereon corresponding to the electrical input/output contacts of the flip chip, wherein the conductive bumps are downward received within the through holes of the ceramic substrate;

a controlled impedance line secured to the conductive bumps;

an electrically conductive heat sink mounted on the flip chip;

a second integrated circuit chip mounted on the heat sink in back-to-back relationship to the flip chip, and including electrical contacts, such that the electrical contacts of the second integrated circuit chip are upward in direction, wherein said flip chip and second integrated circuit chip are adhesively secured to said electrically conductive heat sink by an electrically conductive adhesive to allow back-to-back grounding, and wherein said conductive epoxy is connected to said grounding signal path for back-to-back grounding of said flip chip and said second integrated circuit chip; and

means for electrically connecting the electrical contacts of the second integrated circuit to said conductive patterns formed on the upper side of the ceramic substrate.

8. A package according to claim 7, wherein said conductive bumps are formed from gold.

9. A package according to claim 7, and further comprising a conductive ink plated on the through holes.

10. A package according to claim 7, and further comprising a controlled impedance line secured to the conductive bumps.

11. A package according to claim 7, and further comprising a stepped cut out formed in the ceramic substrate for receiving the flip chip and the second integrated circuit chip.

12. A package according to claim 7, wherein said conductive bumps are formed as epoxy having a conductive material impregnated therein.

13. A package according to claim 7, and further comprising a conductive epoxy that secures together the flip chip, heat sink and second integrated circuit.