Field effect-controlled semiconductor component

• US 6,184,555 B1
• Filed: 12/04/1998
• Issued: 02/06/2001
• Est. Priority Date: 02/05/1996
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Geiger, Heinrich, Strack, Helmut, Tihanyi, Jeno
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/117,636
• Time in Patent Office: 795 Days
• Field of Search: 257/328, 257/341, 257/342, 257/343, 257/329, 257/330, 257/331
• US Class Current: 257/342
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

The invention relates to a field effect-controllable semiconductor component of vertical or lateral design i.e. MOSFETs and IGBTs. In this case, depletion zones and complementary depletion zones of opposite conduction types are introduced in the source-drain load path, in the semiconductor body, i.e. in the inner zone in the case of vertical components and in the drift zone in the case of lateral components, the concentration of the regions doped by the first conduction type corresponding approximately to the concentration of the regions doped by the second conduction type.

Claims

1. Field effect-controlled semiconductor component comprising a semiconductor body with a top surface having:

a) an inner zone of the first conduction type that adjoins the top surface of the semiconductor body;

b) a drain zone that adjoins the inner zone;

c) at least one base zone of the second conduction type that is embedded in the top surface of the semiconductor body;

d) at least one source zone of the first conduction type embedded in the base zone;

e) at least one source electrode that in each case makes contact with the base zone and the source zone embedded therein;

f) a gate electrode that is insulated from the semiconductor body;

g) a multiplicity of depletion zones of the second conduction type and one or more complementary depletion zones of the first conduction type are embedded in the inner zone, the depletion zones floating in the inner zone, the total amount of impurity dopant in the depletion zones being approximately equal to the total amount of impurity dopant in the complementary depletion zones; and

characterized in that

(h) trenches extend from the top surface into the inner zone in the intercell zones, the trenches being filled with insulator and being provided on their trench walls with depletion zones and complementary depletion zones arranged in pairs.

2. The semiconductor component as claimed in claim 1, characterized in that the trenches are of approximately V-shaped design.

3. The semiconductor component as claimed in claim 1, characterized in that the trenches are of approximately U-shaped design.