I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection
First Claim
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1. An input/output circuit formed in a semiconductor material of a first conductivity type, the circuit comprising:
- a first well of a second conductivity type formed in the semiconductor material;
a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;
a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
a first driver transistor connected to a second contact of the first contacts in the second well;
a second driver transistor connected to a second contact of the second contacts in the third well; and
an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts.
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Abstract
The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.
38 Citations
14 Claims
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1. An input/output circuit formed in a semiconductor material of a first conductivity type, the circuit comprising:
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a first well of a second conductivity type formed in the semiconductor material;
a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;
a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
a first driver transistor connected to a second contact of the first contacts in the second well;
a second driver transistor connected to a second contact of the second contacts in the third well; and
an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts. - View Dependent Claims (2, 3, 4, 5, 11)
spaced-apart source and drain regions formed in the first well;
a channel defined between the source and drain regions; and
a gate insulatively disposed over the channel.
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3. The I/O circuit of claim 1 wherein the second driver transistor includes:
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spaced-apart source and drain regions formed in the semiconductor material;
a channel defined between the source and drain regions; and
a gate insulatively disposed over the channel.
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4. The I/O circuit of claim 1 wherein the first well includes:
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a buried well formed in the semiconductor material having a top surface and a bottom surface, the bottom surface of the buried well being lower than the bottom surface of the third well; and
a top well formed in the semiconductor material, the top well having a bottom surface that contacts the top surface of the buried well.
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5. The method of claim 4 wherein the second well is isolated from the semiconductor material by the buried and top wells.
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11. The I/O circuit of claim 1 and further comprising:
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a first diode connected to a supply rail and the I/O pad; and
a second diode connected to the I/O pad and ground.
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6. An input/output circuit formed in a semiconductor material of a. first conductivity type, the circuit comprising:
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a first well of a second conductivity type formed in the semiconductor material;
a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;
a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
a fourth well of a second conductivity type formed in the semiconductor material;
a fifth well of the first conductivity type formed in the fourth well, the fifth well having a dopant concentration;
an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
a first driver transistor connected to a second contact of the first contacts in the second well;
a second driver transistor connected to a second contact of the second contacts in the third well; and
an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts. - View Dependent Claims (7, 8, 9, 10)
spaced-apart source and drain regions formed in the first well;
a channel defined between the source and drain regions; and
a gate insulatively disposed over the channel.
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8. The I/O circuit of claim 6 wherein the second driver transistor includes:
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spaced-apart source and drain regions formed in the semiconductor material;
a channel defined between the source and drain regions; and
a gate insulatively disposed over the channel.
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9. The I/O circuit of claim 6 wherein the first well includes:
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a buried well formed in the semiconductor material having a top surface and a bottom surface, the bottom surface of the buried well being lower than the bottom surface of the third well; and
a top well formed in the semiconductor material, the top well having a bottom surface that contacts the top surface of the buried well.
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10. The I/O circuit of claim 6 wherein the second well is isolated from the semiconductor material by the buried and top wells.
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12. A method for forming an input/output circuit in a semiconductor material of a first conductivity type, the method comprising the steps of:
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forming a first well of a second conductivity type in the semiconductor material;
forming a second well of the first conductivity type in the first well, the second well having a dopant concentration;
forming a pair of spaced-apart first contacts of the first conductivity type in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;
forming a third well of the second conductivity type in the semiconductor material, the third well having a dopant concentration, and a bottom surface;
forming a pair of spaced-apart second contacts of the second conductivity type in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;
forming an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;
forming a first driver transistor connected to a second contact of the first contacts in the second well;
forming a second driver transistor connected to a second contact of the second contacts in the third well; and
forming an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts. - View Dependent Claims (13, 14)
forming a buried well in the semiconductor material, the buried well having a top surface and a bottom surface, the bottom surface of the buried well being lower than the bottom surface of the third well; and
forming a top well in the semiconductor material, the top well having a bottom surface that contacts the top surface of the buried well.
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14. The method of claim 12 wherein the second well is isolated from the semiconductor material by the buried and top wells.
Specification