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I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection

  • US 6,184,557 B1
  • Filed: 01/28/1999
  • Issued: 02/06/2001
  • Est. Priority Date: 01/28/1999
  • Status: Expired due to Term
First Claim
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1. An input/output circuit formed in a semiconductor material of a first conductivity type, the circuit comprising:

  • a first well of a second conductivity type formed in the semiconductor material;

    a second well of the first conductivity type formed in the first well, the second well having a dopant concentration;

    a pair of spaced-apart first contacts of the first conductivity type formed in the second well, the first contacts having a dopant concentration that is greater than the dopant concentration of the second well;

    a third well of the second conductivity type formed in the semiconductor material, the third well having a dopant concentration, and a bottom surface;

    a pair of spaced-apart second contacts of the second conductivity type formed in the third well, the second contacts having a dopant concentration that is greater than the dopant concentration of the third well;

    an I/O pad connected to a first contact of the first contacts in the second well, and a first contact of the second contacts in the third well;

    a first driver transistor connected to a second contact of the first contacts in the second well;

    a second driver transistor connected to a second contact of the second contacts in the third well; and

    an internal circuit connected to the second contact of the first contacts, and the second contact of the second contacts.

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