Constraining ring for use in electronic packaging

• US 6,184,589 B1
• Filed: 11/18/1998
• Issued: 02/06/2001
• Est. Priority Date: 11/08/1996
• Status: Expired due to Term

• Current Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Original Assignee: David A. Hanson, David B. Noddin, John J. Budnaitis, Mark F. Sylvester, Paul J. Fischer, William George Petefish
• Inventors: Hanson, David A., Fischer, Paul J., Petefish, William George, Budnaitis, John J., Noddin, David B., Sylvester, Mark F.
• Primary Examiner(s): LAM, CATHY FONG FONG
• Application Number:
  US09/195,052
• Time in Patent Office: 811 Days
• Field of Search: 257/924, 257/700, 257/701
• US Class Current: 257/690
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/07811 Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 428/24917 : including metal layer
• CPC Class Codes: Y10T 428/24942 : including components having same physical characteristic in differing degree

Abstract

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Claims

1. A constraining ring for use in combination with an interconnect substrate comprising:

a planar member having first and second opposite surfaces, outer peripheral edges and a central opening;

the first surface being connectable to a surface of the substrate with the central opening positioned over a chip-mounting area of the substrate surface;

the planar member having a coefficient of thermal expansion (CTE) that approximately matches the CTE of the substrate; and

a capacitor formed on the second surface of the planar member.

2. A constraining ring according to claim 1, wherein the capacitor includes a first conductive layer formed on at least a portion of the second surface of the planar member, a first dielectric layer formed on at least a portion of the first conductive, a second conductive layer formed on at least a portion of the first dielectric layer, and a second dielectric layer formed on the second conductive layer, the first and second conductive layers forming electrodes of the capacitor.

3. A constraining ring according to claim 1, wherein the capacitor includes a first dielectric layer formed on the second surface of the constraining ring, a first conductive layer formed on at least a portion of the first dielectric layer, a second dielectric layer formed on at least a portion of the first conductive layer, a second conductive layer formed on at least a portion of the second dielectric layer, and a third dielectric layer formed on at least a portion of the second conductive layer, the first and second conductive layers forming electrodes of the capacitor.

4. A constraining ring according to claim 3, further comprising at least one thin film resistor formed on the capacitor.

5. A constraining ring according to claim 4, wherein the thin film resistor includes a thin film layer made of a material having a predetermined resistance and being formed on the surface of the third dielectric layer, and a dielectric coating formed on the thin film layer.

6. A constraining ring according to claim 1, wherein the second surface of the planar member is electrically conductive, and the constraining ring further includes a first dielectric layer formed on the second surface of the constraining ring, a first conductive layer formed on the first dielectric layer, the second surface of the constraining ring and the first conductive layer forming electrodes of a capacitor.

7. A constraining ring according to claim 1, wherein the second surface of the planar member is electrically conductive, and the constraining ring further includes a first dielectric layer formed on the second surface of the planar member, a first conductive layer formed on at least a portion of the first dielectric layer, and a second dielectric layer formed on at least a portion of the first conductive layer, the second surface of the constraining ring and the first conductive layer forming electrodes of a capacitor.