Look-up table based logic element with complete permutability of the inputs to the secondary signals

• US 6,184,707 B1
• Filed: 10/07/1998
• Issued: 02/06/2001
• Est. Priority Date: 10/07/1998
• Status: Expired due to Term

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group), Altera Corporation (Intel Corporation)
• Inventors: Butts, Michael R., Patel, Rakesh H., Sample, Stephen P., Norman, Kevin A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/168,307
• Time in Patent Office: 853 Days
• Field of Search: 326/37, 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/39
• CPC Class Codes: G05B 2219/25268 PLD programmable logic device
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).

Claims

1. In a programmable logic device, a logic element comprising:

a memory;

a multiplexor having a plurality of control inputs and a plurality of data inputs, the plurality of data inputs being coupled to said memory;

a storage block coupled to said multiplexor, wherein said storage block stores an output of said multiplexor;

a first plurality of inputs coupled to said control inputs of said multiplexor, said first plurality of inputs being sufficient in number to uniquely select between each of the plurality of data inputs to said multiplexor, each of said first plurality of inputs being programmably coupled to said storage block;

a combinatorial output, coupled to said multiplexor; and

a registered output, coupled to said storage block.

2. The logic element of claim 1 said storage block being programmably configurable as a latch in a first mode, wherein said latch is responsive to a level-sensitive input, and said storage block being programmably configurable as a register in a second mode, wherein said register is responsive to an edge-triggered input.

3. A system comprising a logic element as recited in claim 1.

4. The logic element of claim 1 further comprising a programmable delay block coupled between said multiplexor and said storage block.

5. The logic element of claim 1 wherein each of said

first plurality of inputs are programmably coupled to a clear input of said storage block.

6. The logic element of claim 1 wherein each of said

first plurality of inputs are programmably coupled to a preset input of said storage block.

7. The logic element of claim 1 wherein each of said

first plurality of inputs are programmably coupled a clock enable input of said storage block.

8. The logic element of claim 1 wherein each of said

first plurality of inputs are programmably coupled to a clock input of said storage block.

9. The logic element of claim 8 further comprising:

a second plurality of inputs programmably coupled to said clock input of said storage block.

10. The logic element of claim 1 further comprising:

a diagnostic shadow latch coupled to said memory and said storage block, wherein said diagnostic shadow latch stores and provides diagnostic data.

11. The logic element of claim 1 further comprising:

a diagnostic shadow latch coupled to an input of said storage block and an output of said storage block, wherein said diagnostic shadow latch stores and provides diagnostic data.

12. The logic element of claim 1 further comprising:

a diagnostic shadow latch coupled to a plurality of configuration loading pins for said memory, wherein said diagnostic shadow latch stores and provides diagnostic data.

13. The system of claim 3 further comprising a secondary logic block with inputs coupled to the first plurality of inputs and the multiplexor and an output programmably coupled to the storage block.

23. The logic element of claim 1 wherein the memory is a random access memory.

14. A logic element for an integrated circuit, comprising:

a memory having a plurality of outputs;

a multiplexor having a plurality of control inputs and a plurality of data inputs, the plurality of data inputs being coupled to said memory;

a storage block coupled to said multiplexor, wherein said storage block stores an output of said multiplexor;

a first plurality of inputs coupled to said control inputs of said multiplexor, said first plurality of inputs being sufficient in number to uniquely select between each of the plurality of data inputs to said multiplexor, each of said first plurality of inputs being programmably coupled to said storage block;

a second plurality of inputs coupled to said storage block providing complementary signals of each of said first plurality of inputs, respectively;

a combinatorial output, coupled to said multiplexor; and

a registered output, coupled to said storage block.

15. The logic element of claim 14 further comprising a secondary logic block programmably coupled to each of the first plurality of inputs and each of the second plurality of inputs and the multiplexor and providing an output to the storage block.

16. The logic element of claim 14 wherein the each of the first plurality of inputs and each of the second plurality of inputs are coupled to a clear input of the storage block.

17. The logic element of claim 16 wherein each of the first plurality of inputs and each of the second plurality of inputs are coupled to a preset input of the storage block.

18. The logic element of claim 14 wherein each of the first plurality of inputs are programmably coupled to a clock input of the storage block.

19. The logic element of claim 18 wherein each of the second plurality of inputs are programmably coupled to the clock input of the storage block.

20. The logic element of claim 19 further comprising a third plurality of inputs programmably coupled to the clock input of the storage block.

21. The logic element of claim 20 further comprising a fourth plurality of inputs programmably coupled to the clock input of the storage block, the fourth plurality of inputs providing a complementary signal for each of the third plurality of inputs, respectively.

22. The logic element of claim 21 further comprising a programmable delay element coupled between the multiplexor and the storage block.

24. The logic element of claim 14 wherein the memory is a random access memory.

25. In a programmable logic device, a logic element comprising:

a memory for storing a plurality of data entries;

a storage element coupled to the memory;

a plurality of control inputs for selecting at least one of said data entries, said plurality of control inputs being programmably coupled to said storage element;

a first output port for outputting said selected data entry; and

a second output port coupled to said storage element for outputting said stored data entry.

26. The logic element of claim 25 further comprising a multiplexer for selecting between signals on said first and second output ports.

27. The logic element of claim 26 further comprising a secondary logic block for performing a logic function on said selected data entry.