Scalable architecture for high density CPLDS having two-level hierarchy of routing resources

• US 6,184,713 B1
• Filed: 06/06/1999
• Issued: 02/06/2001
• Est. Priority Date: 06/06/1999
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Stanley, Claudia A., Agrawal, Om P., Metzger, Larry R., Simon, Robert A., He, Xiaojie (Warren), Ilgenstein, Kerry A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/326,940
• Time in Patent Office: 611 Days
• Field of Search: 326/41, 326/40, 326/39, 326/38, 326/37
• US Class Current: 326/41
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM'"'"'s). An even number of Super Logic Blocks (SLB'"'"'s) are coupled to each SSM. Each SSM and its SLB'"'"'s define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT'"'"'s) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.

Claims

1. A monolithic, High-Density Complex Programmable Logic Device (HCPLD) for programmably implementing designs having parallel data words that are at least B bits wide, where B is an integer equal to or greater than 32, said HCPLD having at least 64 I/O terminals for communicating with external circuitry and at least 256 result-storing macrocells, said HCPLD further comprising:

(a) a two-tiered hierarchical switch matrix construct having a Global Switch Matrix (GSM) and a plurality of Segment Switch Matrices (SSM'"'"'s) operatively coupled to the GSM; and

(b) for each one of the SSM'"'"'s, a respective plurality of at least four programmable, Super Logic Blocks (SLB'"'"'s) operatively coupled to the one SSM such that each SLB can receive in parallel a first number, K of SLB input signals from the SSM and such that each SLB can supply in parallel a second number, M of SLB output signals to the SSM, where said combination of each one SSM and its respective plurality of SLB'"'"'s defines a segment;

(b.1) wherein the number, K of SLB input signals is greater than 112.5% of B, the bit-width of said to-be-implemented designs; and

(b.2) wherein the number, M of SLB output signals per SLB is greater than B divided by the number of SLB'"'"'s in each segment.

2. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein said number of result-storing macrocells is at least 512.

3. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein:

(b.3) B, the bit-width of said to-be-implemented designs is at least 64.

4. The High-Density Complex Programmable Logic Device (HCPLD) of claim 3 wherein:

(b.1a) the number, K of SLB input signals is at least 125% of B, the bit-width of said to-be-implemented designs.

5. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein:

(b.1a) the number, K of parallel SLB input signals is at least 80.

6. The High-Density Complex Programmable Logic Device (HCPLD) of claim 5 wherein:

(b.2a) wherein the number, M of SLB output signals per SLB is at least 32.

7. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein:

each SLB has at least 32 macrocells and at least 16 I/0 pads which feedback both to the local SSM and the GSM;

each SSM has dedicated for intra-segment communications, at least as many longlines as there are macrocells and I/O pads in the corresponding segment, thereby assuring that every macrocell signal (MFB) and I/O signal (IFB) of the corresponding segment can be simultaneously transmitted through the SSM.

8. The High-Density Complex Programmable Logic Device (HCPLD) of claim 7 wherein:

the GSM is sufficiently wide and each SSM further has, as dedicated for inter-segment communications, at least as many longlines as there are macrocells and I/O pads in each of plural segments, to thereby assure that every macrocell signal (MFB) and I/O signal (IFB) of a first segment can be simultaneously transmitted through the GSM from the first segment to another of the plural segments.

9. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein:

each SLB has at least 3 ways of transmitting a feedback signal through its local SSM and then back to either itself or another SLB of the same segment so that CPLD configuring software is thereby given good flexibility to route intra-segment signals.

10. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein:

each SLB has at least 12 ways of transmitting a feedback signal (MFB or IFB) through the GSM and then back to either its own segment or to another segment.

11. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein said HCPLD has at least 128 I/O terminals for communicating with said external circuitry.

12. The High-Density Complex Programmable Logic Device (HCPLD) of claim 1 wherein each SLB has at least one nonburied pad that does provide for communicating with said external circuitry and at least one buried pad that does not provide for communicating with said external circuitry.

13. A method for granularly implementing with an High-Density Complex Programmable Logic Device (HCPLD), designs that are either 16-bits wide or 32-bits wide or 64-bits wide,

where said HCPLD is a monolithic device having at least 64 I/O terminals for communicating with external circuitry and at least 256 result-storing macrocells, and said HCPLD further comprises:

(O.1) a two-tiered hierarchical switch matrix construct having a Global Switch Matrix (GSM) and an even-numbered plurality of Segment Switch Matrices (SSM'"'"'s) operatively coupled to the GSM; and

(O.2) for each one of the SSM'"'"'s, a respective even-numbered plurality of at least four programmable, Super Logic Blocks (SLB'"'"'s) operatively and symmetrically coupled to the one SSM such that each SLB can receive in parallel a first number, K of SLB input signals from the SSM and such that each SLB can supply in parallel a second number, M of SLB output signals to the SSM, where said combination of each one SSM and its respective plurality of SLB'"'"'s defines a segment,

said method comprising the step of selecting at least one segment and further comprising one or more appropriate further ones of the steps of;

(a) using the symmetry of the selected at least one segment to fold together the at least four SLB'"'"'s of that respective segment for implementing a 64-bits wide design;

(b) using the symmetry of the selected at least one segment to further select and fold together at least two SLB'"'"'s of that respective segment for implementing a 32-bits wide design; and

(c) using the symmetry of the selected at least one segment to further select and implement with one SLB of that respective segment, a 16-bits wide design.

14. The granularly implementing method of claim 13 and further comprising the step of:

(d) borrowing one or more pads from a first of said segments for transmitting a respective one or more input signals to a second of said segments.

15. The granularly implementing method of claim 13 and further comprising the step of:

(d) borrowing one or more pads and output buffers from a first of said segments for transmitting by way of said borrowed pads and output buffers, a respective one or more output signals of a second of said segments.

16. A monolithic, Complex Programmable Logic Device (CPLD) for programmably implementing designs, where such designs can have parallel data or address words that are at least B bits wide, where B is an integer equal to or greater than 32, said CPLD having at least 64 I/O terminals for communicating with external circuitry, said CPLD further comprising:

(a) a plurality of configurable segments where each such segment includes;

(a.1) a plurality of super logic blocks (SLB'"'"'s), where each said SLB has a first number of logic block input lines for receiving SLB input signals, said first number being equal to at least B times 112.5%, and where each said SLB has a second number of logic block output lines for outputting SLB output signals; and

(a.2) a segment switch matrix (SSM) for receiving as a first subset of SSM-received signals, a plurality of intra-segment feedback signals from sources within the segment and for programmably coupling any one to all of the SSM-received intra-segment feedback signals each to at least a third number of the logic block input lines in the segment, where the SSM-received intra-segment feedback signals include the SLB output signals of all of the SLB'"'"'s in the segment and where said SSM has a fourth number of longlines for transmitting SSM-received signals to the SLB'"'"'s of its respective segment, said SSM further having a fifth number of shortlines crossing with its longlines to define crosspoints, said fifth number being equal at least to the number of SLB'"'"'s in the segment multiplied by said first number, and said crosspoints of the SSM being partially-populated so as to at least provide said third number of ways for an SLB output signal to route through the SSM to an SLB input line within the segment; and

(b) a programmably configurable global switch matrix (GSM) coupled to receive SLB output signals from each of said SLB'"'"'s and to selectively route such GSM-received signals to the SSM'"'"'s of said segments as a second subset of the SSM-received signals,

wherein the fourth number of longlines in each SSM includes a sixth number of longlines for carrying the second subset of SSM-received signals that are routed to the SSM from the GSM.

17. The CPLD of claim 16 wherein B is an integer equal to or greater than 64.

18. The CPLD of claim 16 wherein said first number is equal to at least B times 125%.

19. The CPLD of claim 18 wherein B is an integer equal to or greater than 64.

20. The CPLD of claim 19 wherein each SLB has a seventh number of macrocells for producing respective macrocell feedback signals (MFBs) and

wherein said SLB output signals of each logic block are defined at least by said MFBs of the logic block.

21. The CPLD of claim 20 wherein said number of macrocells in each SLB is at least 32.

22. The CPLD of claim 20 wherein for each SLB there is within the corresponding segment, an eighth number of buried or nonburied I/O elements for transmitting respective I/O feedback signals (IFBs), where said SSM-received signals of the corresponding segment are defined at least by said MFBs and IFBs of the constituent logic blocks (SLBs) of the segment.

23. The CPLD of claim 16 wherein at least one segment further includes nonburied I/O elements for transmitting respective I/O signals between the at least one segment and external pins such that the at least one segment can operate as a self-contained and independent mini-CPLD having a pin-to-pin, one-pass processing delay of no more than about 7.5 nanoseconds (nS).

24. The CPLD of claim 23 wherein there are at least two segments with said capability of each operating as a self-contained and independent mini-CPLD, and wherein an external input signal received by a first of the segments can be transmitted by way of the GSM to a second of the segments for output by a pin of the second segment, and where such a global operation can exhibit a pin-to-pin, one-pass processing delay of no more than about 10 nS.

25. The CPLD of claim 16 wherein:

(a.3) each SLB can produce complex, sum-of-products function signals that conform to the expressive form;

26. The CPLD of claim 25 wherein:

(a.5) for each SLB the corresponding segment includes one or more I/Oelements associated with the SLB and a respective Output Switch Matrix (OSM), where the respective OSM is structured for programmably and uniformly routing one of a respective subset of SLB output signals to one or more I/O elements of the segment so that for each SLB therein, the segment can provide a commensurate degree of PinOut-Consistency.

27. The CPLD of claim 26 wherein:

(a.5a) the number of different I/O elements to which each OSM can programmably route its respective subset of SLB output signals is at least four.

28. The CPLD of claim 26 wherein:

(a.5a) the number of different I/O elements to which each OSM can programmably route its respective subset of SLB output signals is at least eight.

29. The CPLD of claim 25 wherein

(a.4) each segment can provide Speed-Consistency for one-pass production and feedback use of the complex, sum-of-products function signals produced therein.

30. The CPLD of claim 29 wherein:

(b.1) the GSM can provide Speed-Consistency for one-pass production and global feedthrough use of the complex, sum-of-products function signals produced by different ones of the segments of the CPLD.

31. The CPLD of claim 16 wherein:

(a.3) each SLB can produce complex, sum-of-products function signals that conform to the expressive form;

32. The CPLD of claim 31 wherein:

(a.4) each of the plural segments can provide Speed-Consistency for one-pass production or feedback use of the complex, sum-of-products or product of sums function signals produced therein so as to provide predictable sameness of timing for such one-pass production or feedback use irrespective of which one or more segments is employed for such one-pass production or feedback use.

33. The CPLD of claim 29 wherein:

(b.1) the GSM can provide Speed-Consistency for one-pass production and global feedthrough use of the complex, sum-of-products or product of sums function signals produced by different ones of the segments of the CPLD.

34. The CPLD of claim 31, wherein L2 is at least as large as L1.

37. The CPLD of claim 32 wherein:

said segments are disposed in a substantially symmetrical pattern about the GSM such the combination of the GSM and segments at least approximates a regular polygon.

38. The CPLD of claim 37 wherein:

each SSM includes a plurality of longlines for broadcasting global and intra-segment signals across the respective segment; and

pairs of segments are aligned such that global signal carrying ones of the longlines of their respective SSM'"'"'s are co-linear.

39. The CPLD of claim 32 wherein:

(b.2) for each given one of the SSM'"'"'s, the GSM includes a plurality of P;

1 multiplexers for programmably routing signals from the GSM to the given SSM, P being an integer greater than 2 but substantially less than the number of longlines in the GSM;

(b.2a) the P PIP'"'"'s within respective P;

1 multiplexers are confined to a predefined, plural number of GSM output bands; and

(b.2b) the P PIP'"'"'s of successive P;

1 multiplexers are distributed in a random or pseudo-random manner among the GSM output bands to which they are confined.

35. A monolithic, Complex Programmable Logic Device (CPLD) having a plurality of I/O terminals for communicating with external circuitry and at least 256 result-storing macrocells, said CPLD further comprising:

(a) a two-tiered hierarchical switch matrix construct having a Global Switch Matrix (GSM) for carrying global signals and a plurality of Segment Switch Matrices (SSM'"'"'s) operatively coupled to receive the global signals from the GSM; and

(b) for each one of the SSM'"'"'s, a respective plurality of programmable, Super Logic Blocks (SLB'"'"'s) operatively coupled to the one SSM such that each SLB can receive in parallel a first number, K of SLB input signals from the SSM and such that each SLB can supply in parallel a second number, M of SLB output signals to the SSM, where said combination of each one SSM and its respective plurality of SLB'"'"'s defines a segment, where each of the SLB'"'"'s includes therein a subset of the result-storing macrocells; and

(b.1) wherein each SLB is operatively coupled to the GSM such that the SLB can further supply in parallel at least said second number, M of SLB output signals to the GSM.

36. The CPLD of claim 35 wherein:

the GSM includes a plurality of longlines for globally broadcasting signals; and

(b.1a) for each GSM longline, a plurality of multiplexers are provided and coupled distributively to that longline of the GSM for programmably routing SLB output signals from corresponding SLB'"'"'s to the GSM longline.

40. A monolithic, Complex Programmable Logic Device (CPLD) having a first plurality of I/O terminals for communicating with external circuitry and a second plurality of at least 256 result-storing macrocells, said CPLD further comprising:

(a) a two-tiered hierarchical and programmably-configurable switch matrix construct consisting of a Global Switch Matrix (GSM) for carrying global signals and a third plurality of Segment Switch Matrices (SSM'"'"'s) each for carrying respective intra-segment signals and at least a respective subset of the global signals, said SSM'"'"'s being operatively coupled the GSM for receiving respective global signals from the GSM; and

(b) for each one of the SSM'"'"'s, a respective fourth plurality of programmable, Super Logic Blocks (SLB'"'"'s) operatively coupled to the corresponding one SSM such that each SLB can receive in parallel a first number, K of SLB input signals from its corresponding SSM and such that each SLB can supply in parallel a second number, M of SLB output signals for coupling to the SSM, where said combination of each one SSM and its corresponding fourth plurality of SLB'"'"'s defines a segment;

(b.1) wherein two or more of the SLB'"'"'s has a respective subset of the first plurality of I/O terminals associated therewith;

(b.2) wherein each SLB has a respective subset of the second plurality of result-storing macrocells included therewithin; and

(b.3) wherein each respective SLB is operatively coupled to the GSM so that the respective SLB can further supply in parallel at least said second number, M of SLB output signals to the GSM.

41. The CPLD of claim 40 wherein

(b.3a) each SLB has a respective set of I/O input buffers and output buffers associated therewith, said I/O terminals being coupled to at least a subset of said I/O buffers; and

(b.4) each respective I/O input buffer is operatively coupled to the GSM so that the respective I/O input buffers can further supply in parallel, a corresponding plurality of I/O input signals to the GSM.