Parallel-to-parallel converter including common multiple register

• US 6,184,808 B1
• Filed: 09/23/1998
• Issued: 02/06/2001
• Est. Priority Date: 09/24/1997
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakamura, Kazuyuki
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/159,392
• Time in Patent Office: 867 Days
• Field of Search: 341/59, 341/58, 341/101, 341/100, 341/95, 370/536, 340/347
• US Class Current: 341/95
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

In a parallel-to parallel converter for converting an “m”-bit parallel signal into an “n”-bit parallel signal, a common multiple register has a bit width which is a common multiple of “m” and “n”. An input selector is connected to an input of the common multiple register, and writes the “m”-bit parallel signal into the common multiple register at a predetermined frequency. An output selector is connected to an output o f the common multiple register, and reads the “n”-bit parallel signal from the common multiple register at a frequency equal to m/n times the predetermined frequency.

Claims

1. A parallel-to-parallel converter for converting an “

m”

-bit parallel signal into an “

n”

-bit parallel signal, comprising;

a common multiple register having a bit width which is a common multiple of “

m” and

“

n”

;

an input selector, connected to an input of said common multiple register, for writing said “

m”

-bit parallel signal into said common multiple register at a predetermined frequency; and

an output selector, connected to an output of said common multiple register, for reading said “

n”

-bit parallel signal from said common multiple register at a frequency equal to m/n times said predetermined frequency.

2. The parallel-to-parallel converter as set forth in claim 1, wherein one of said “

m” and

“

n”

is the i-th power of 2 (i=1, 2, --- ).

3. The parallel-to-parallel converter as set forth in claim 1, wherein a timing of writing said “

m”

-bit parallel signal into said common multiple register is different from a timing of reading said “

n”

-bit parallel signal from said common multiple register.

4. The parallel-to-parallel converter as set forth in claim 1, further comprising a clock signal generation circuit, said clock signal generation circuit comprising;

an “

N”

-frequency divider for dividing a frequency of a clock signal by “

N”

,

a first ring counter, connected to said “

N”

-frequency divider, for counting an output signal of said “

N”

-frequency divider;

an “

M”

-frequency divider for dividing the frequency of said clock signal by “

M”

, wherein M/N is equal to m/n; and

a second ring counter, connected to said “

M”

-frequency divider, for counting an output signal of said “

M”

-frequency divider;

said input selector comprising an input register, connected to said “

N”

-frequency divider, for storing said “

m”

-bit parallel signal in synchronization with the output signal of said “

N”

-frequency divider,

said output selector comprising an output register, connected to said “

M”

-frequency divider, for storing said “

n”

-bit parallel signal in synchronization with the output signal of said “

M”

-frequency divider,

said common multiple register being connected to said first and second ring counters, a write operation upon said common multiple register being carried out in synchronization with an output signal of said first ring counter, a read operation upon said common multiple register being carried out in synchronization with an output signal of said second ring counter.

11. The parallel-to-parallel converter as set forth in claim 1 wherein m/n≠

2 and n/m≠

2.

5. A parallel-to serial converter circuit comprising:

a parallel-to-parallel converter for converting a “

m”

-bit parallel signal into a “

n”

-bit parallel signal where “

n”

is the i-th power of 2 (i=1,2,---); and

a tree-type parallel-to-serial converter, connected to said parallel-to parallel converter, for converting said “

n”

-bit parallel signal into a serial signal,

said parallel-to-parallel converter comprising;

a common multiple register having a bit width which is a common multiple of “

m” and

“

n”

;

an input selector, connected to an input of said common multiple register, for writing said “

m”

-bit parallel signal into said common multiple register at a predetermined frequency; and

an output selector, connected to an output of said common multiple register, for reading said “

n”

-bit parallel signal from said common multiple register at a frequency equal to m/n times said predetermined frequency.

12. The parallel-to-serial converter as set forth in claim 5 wherein m/n≠

2 and n/m≠

2.

6. A serial-to-parallel converter circuit comprising:

a tree-type serial-to-parallel converter for converting a serial signal into an “

m”

-bit parallel signal where “

m”

is the i-th power of 2 (i=1,2, --- ); and

a parallel-to-parallel converter for converting said “

m”

-bit parallel signal into a “

n”

-bit parallel signal, said parallel-to-parallel converter comprising;

a common multiple register having a bit width which is a common multiple of “

m” and

“

n”

;

an input selector, connected to an input of said common multiple register, for writing said “

m”

-bit parallel signal into said common multiple register at a predetermined frequency; and

an output selector, connected to an output of said common multiple register, for reading said “

n”

-bit1parallel signal from said common multiple register at a frequency equal to m/n times said predetermined frequency.

13. The serial-to-parallel converter as set forth in claim 6 wherein m/n≠

2 and n/m≠

2.

7. A parallel-to-parallel converter for converting an “

m”

-bit input signal having a predetermined frequency into an “

n”

-bit output signal having a frequency m/n times said predetermined frequency, one of “

m” and

“

n”

being the i-th power of 2(i=1,2, . . .),

said converter including a common multiple register having a bit width which is a common multiple of said “

m” and

said “

n”

.

14. The parallel-to-parallel converter as set forth in claim 7 wherein m/n≠

2 and n/m≠

2.

8. A parallel-to-parallel converter comprising:

a holding means constituted by a number of registers, the number being equal to a common multiple of “

m” and

“

n”

;

a write means for writing an “

m”

-bit input signal into said registers with an input frequency; and

a read means for reading an “

n”

-bit output signal from said registers with a frequency equal to m/n times said input frequency.

9. The parallel-to-parallel converter as set forth in claim 8, further comprising a control means for controlling and differentiating a timing of writing said “

m”

-bit input signal into said registers and a timing reading said “

n”

-bit output signal from said registers.

10. The parallel-to-parallel converter as set forth in claim 8, where said write means comprises an input register and said read means comprises an output register,

said parallel-to-parallel converter further comprising:

an “

N”

-frequency divider means for dividing an input frequency by “

N”

,

output registers arranged at the output side of said holding means and an “

M”

-frequency divider means for dividing said input frequency by “

M”

, where M/N is equal to m/n,

said write means being adapted to write data stored in said input register into said registers by means of an output signal of said “

N”

-frequency divider means,

said read means being adapted to read data stored in said registers to said output register by means of an output signal of said “

M”

-frequency divider means.

15. The parallel-to-parallel converter as set forth in claim 8 wherein m/n≠

2 and n/m≠

2.