MEMS based tile assemblies and methods of fabrication

• US 6,185,107 B1
• Filed: 12/23/1998
• Issued: 02/06/2001
• Est. Priority Date: 12/23/1998
• Status: Expired due to Fees

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Wen, Cheng P.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): FOSTER, DAVID A
• Application Number:
  US09/220,086
• Time in Patent Office: 776 Days
• Field of Search: 361/803, 361/760, 361/762, 361/765, 361/783, 257/684, 257/773, 257/774, 257/777, 257/778, 174/250, 174/255, 174/256, 174/260, 174/261, 174/262, 174/266, 228/180.22
• US Class Current: 361/803
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 3/002 Aligning microparts

Abstract

Structures and methods that provide for the vertical alignment of and electrical interconnection of MEMS tiles using metallized elastic spheres and precision pyramid shaped pits etched on the surface of silicon substrates. The methods of producing large area, multi-tile (substrate) structures permit fabrication of phased array antenna transmit/receive subsystems, for example, requiring precision, vertical electrical (DC and RF) interconnects between tiles and frames stacked on top of one another. Metallized, back-to-back, inverted pyramid shaped, vertical via structures are fabricated on high resistivity silicon tiles using micro-electronics mechanical system (MEMS) techniques. Slightly oversize, metallized, elastic spheres are squeezed between two inverted pyramid-shaped indentations to provide electrical conduction and accurate alignment between the substrates.

Claims

1. A MEMS based tile assembly comprising:

lower and upper silicon substrates;

flip chip MMIC devices attached to the lower and upper silicon substrates; and

a plurality of silicon frames interconnecting the lower and upper silicon substrates that provide vertical electrical interconnects between the silicon substrates and the flip chip MMIC devices that comprise;

a plurality of pyramid shaped etched pits formed in opposite surfaces of the silicon frames;

via holes formed through the silicon frames interconnecting the pyramid shaped etched pits;

V-shaped, etched grooves formed in the silicon substrates;

metallization formed on inner surfaces of the etched pits, the etched grooves and the via holes to form metallized vias; and

conducting elastic spheres wedged between adjacent metallized etched pits and etched grooves.

2. The tile assembly recited in claim 1 wherein the diameter of the elastic spheres is large enough so that they are slightly compressed at contact areas at surface of the spheres and the inner wall of the etched inverted pyramids formed by the V-shaped, etched grooves.

3. The tile assembly recited in claim 1 wherein the spheres are elastic enough so that opposing surfaces of the silicon tiles are pressed against one another with the spheres wedged between them.

4. The tile assembly recited in claim 2 wherein the spheres are elastic enough so that opposing surfaces of the silicon tiles are pressed against one another with the spheres wedged between them.