Access structure for high density read only memory

• US 6,185,121 B1
• Filed: 02/26/1998
• Issued: 02/06/2001
• Est. Priority Date: 02/26/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: OʼNeill, Jay Henry
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/031,010
• Time in Patent Office: 1,076 Days
• Field of Search: 365/94, 365/51, 365/52, 365/63, 365/230.06, 257/210, 257/211
• US Class Current: 365/94
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A high density read only memory structure is arranged to have the decoders and selectors which are used to access the read only memory arrays in a layer which is above and/or below the read only memory array layers. Note that by layer it is meant a substantially planar structure with some thickness in which the circuitry that makes up particular functionality resides. Thus, the inefficient two-dimensional structure of the prior art is folded over to create a compact read only memory device with a three-dimensional structure. Connection of the decoders to the rows is not limited to the ends of the rows, but instead may be made at any point along the rows. Similarly, connection of the selectors to the columns is not limited to the ends of the columns, but instead may be made at any point along the columns. Advantageously, additional circuitry is not required on the periphery of the memory array, so that a smaller overall memory device is achieved. In addition, in order to reduce cross talk when reading the memory array with a low impedance amplifier, the memory is addressed using a single active row, and, it is read only one column at a time.

Claims

1. A read only memory, comprising:

a two-dimensional array of read only memory cells in a layer; and

a row decoder for selecting a portion of said two-dimensional array of memory cells, said row decoder being located in a layer that is different from said layer of said two-dimensional array of read only memory cells;

wherein said layer of said row decoders is above at least said layer of said two-dimensional array of read only memory cells.

2. The invention as defined in claim 1 wherein said two-dimensional array of read only memory cells is arranged into said layer and another layer, and wherein said layer of said row decoder is below said other layer of said two-dimensional array of read only memory cells.

3. A read only memory, comprising:

a two-dimensional array of read only memory cells in a layer; and

an output selector for reading information from a portion of said two-dimensional array of memory cells, said output selector being located in a layer that is above said layer of said two-dimensional array of read only memory cells.

4. The invention as defined in claim 3 wherein said output selector is a two-dimensional array of column selectors.

5. The invention as defined in claim 3 wherein said output selector includes an amplifier.

6. The invention as defined in claim 3 wherein only one column is selected by said output selector for each read of said memory array.

7. A read only memory, comprising:

a two-dimensional array of read only memory cells in a layer; and

a memory reading circuit for reading a portion of said two-dimensional array of memory cells, said memory reading circuit being located in a layer that is different from said layer of said two-dimensional array of read only memory cells;

wherein said layer of said memory reading circuit is above at least said layer of said two-dimensional array of read only memory cells.

8. The invention as defined in claim 7 wherein said memory reading circuit includes decode-select circuit.

9. The invention as defined in claim 7 wherein said memory reading circuit includes row drivers.

10. The invention as defined in claim 7 wherein said memory reading circuit includes column selectors.

11. The invention as defined in claim 7 wherein said memory reading circuit includes circuit means for connecting one or more columns of said at least one layer of said two-dimensional array of read only memory cells to ground when said one or more columns are not being selected for reading.

12. The invention as defined in claim 7 wherein said two-dimensional array of read only memory cells is arranged into said layer and another layer, and wherein said layer of said memory reading circuit is below said other layer of said two-dimensional array of read only memory cells.