Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 6,185,122 B1
• Filed: 12/22/1999
• Issued: 02/06/2001
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek, Lee, Thomas H., Johnson, Mark G., Farmwald, P. Michael
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/469,658
• Time in Patent Office: 412 Days
• Field of Search: 365/103, 365/176, 365/180, 365/230.06, 365/105, 365/114, 365/51
• US Class Current: 365/103
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A memory array comprising:

a first plurality of spaced-apart, parallel, substantially coplanar conductors;

a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another; and

a plurality of first memory cells each comprising a first steering element in contact with a first state change element, each cell directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors, the first steering elements being in contact with the second conductors;

a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;

a plurality of second memory cells each comprising a second steering element in contact with a second state change element, each cell directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, the second steering elements being in contact with the second conductors.

2. The array defined by claim 1 wherein first cells and second cells are in vertical alignment with one another.

3. The array defined by claim 1 wherein the first cells and second cells are staggered from one another.

4. The array defined by claim 1 wherein the first and second cells have a generally rectangular cross-section.

5. The array defined by claim 1 wherein the first and second cells comprise polysilicon and silicon dioxide.

6. The array defined by claim 1 wherein the first and second cells comprise polysilicon.

7. The array defined by claim 1 wherein the array is fabricated on a silicon substrate.

8. The array defined by claim 7 includes a first contact extending from one of the second conductors to a first region in the substrate.

9. The array defined by claim 8 including a second contact extending from one of the first conductors to a second region in the substrate.

10. The array defined by claim 1 wherein the first and second conductors include a refractory metal.

11. The array defined by claim 10 wherein the refractory metal is tungsten.

12. The array defined by claim 1 wherein the first and second conductors are a silicide.

59. The memory defined by claims 1, 13 or 58 wherein the state change element is an antifuse.

13. A memory array comprising:

a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1, 3 . . . running in a first direction, the levels in the even numbered levels 2, 4 . . . running in a second direction, generally perpendicular to a first direction, and

a plurality of memory cells each having an input terminal directly connected to a diode and an output terminal with a state change element directly connected between the diode and the output terminal, the cells being disposed between conductors in each of the levels 1, 2, 3, 4 . . . ;

the input terminals of the cells being directly connected to the conductors in the odd numbered levels 1, 3 . . . and the output terminals of the cells being directly connected to the conductors in the even numbered levels 2, 4 . . . .

14. The array defined by claim 13 wherein the cells have a generally rectangular cross-section.

15. The array defined by claim 13 wherein the cells comprise silicon and silicon dioxide.

16. The array defined by claim 13 wherein the conductors of levels 1, 3 . . . are in vertical alignment with one another.

17. The array defined by claim 13 wherein the conductors In one of the sets of levels 1, 3 . . . and levels 2, 4 . . . are staggered in the vertical direction.

18. The array defined by claim 13 wherein the conductors comprise polysilicon.

19. The array defined by claim 13 wherein the array is fabricated on a silicon substrate.

20. The array defined by claim 19 including a contact extending from one of the conductors in the odd numbered levels 1, 3, . . . to the substrate.

21. The array defined by claim 19 including a contact extending from one of the conductors in the even numbered levels 2, 4, . . . to the substrate.

22. The array defined by claim 19 including at least one contact extending from the highest level to the substrate.

23. The array defined by claim 19 wherein a contact is made up of several contacts, one for each of the layers.

24. A process for fabricating a memory array comprising:

(a) forming a first layer of conductive material;

(b) forming a plurality of second layers for defining memory cells on the first layer;

(c) patterning the second layers into a plurality of parallel, spaced-apart strips;

(d) etching the first layer in alignment with the strips formed from the second layers;

(e) forming insulating material between the strips of first layer material and the strips formed from the second layers;

(f) forming a third layer of conductive material on the insulating material and the strips formed from the second layer;

(g) forming a plurality of fourth layers for defining memory cells of the second level;

(h) patterning the fourth layers into a plurality of parallel, spaced-apart strips, the strips formed from the fourth layers running generally perpendicular to the strips formed from the first layer;

(i) etching the third layer and the strips formed from the second layers in alignment with the strips formed from the fourth layers.

25. The process defined by claim 24 including forming a fifth layer of conductive material on the strips formed from the fourth layer;

patterning the fifth layer into a plurality of parallel, spaced-apart conductors running generally perpendicular to the strips in the fourth layer; and

,

etching the strips formed from the fourth layer in alignment with the conductors thereby defining additional memory cells.

26. The process of claim 24 repeating steps (a) through (i).

27. The process defined by claim 26 with the steps of claim 25.

28. The process defined by claim 24 repeating the steps (a) through (i) a plurality of times.

29. The process defined by claim 28 with the steps of claim 25.

30. The process defined by claim 24 wherein a dielectric is applied and a planarization step occurs after the etching of the first layer and prior to the forming of the third layer.

31. The process defined by claim 30 wherein the planarization comprises chemical-mechanical polishing.

32. The process defined by claim 24 including depositing an insulator and etching it back to planarize the structure and opening electrical contacts to the strips formed from the second layer between steps (d) and (e).

33. The process defined by claim 24 wherein the plurality of second layers and plurality of fourth layers each comprise layers of polysilicon and silicon dioxide.

34. The process defined by claim 33 wherein the polysilicon is doped such that each memory cell includes a diode.

35. The process defined by claim 33 wherein the silicon dioxide in each layer forms part of an antifuse.

36. The process defined by claims 24 or 30 wherein a planarization step occurs after the forming of the second layers and before the forming of the third layer.

37. The process defined by claim 36 wherein the planarization is performed by chemical-mechanical polishing.

38. The process defined by claim 36 including forming openings for contacts after the planarization.

39. The process defined by claim 33 wherein the polysilicon is deposited at low temperature using chemical vapor deposition.

40. The process defined by claim 24 including the deposition of a barrier metal layer after the forming of the first layer and prior to the forming of the second layers.

41. The process defined by claim 24 including the deposition of a barrier metal layer after the forming of the third layer and prior to the forming of the fourth layer.

42. The process defined by claim 24 wherein the fabrication includes the fabrication of contacts and where contact openings are made followed by the deposition of silicon into the openings.

43. The process defined by claim 24 including the use of ion implanted silicon.

44. The process defined by claim 24 including the use of in-situ doped silicon.

45. The process defined by claim 44 wherein the silicon is deposited using LPCVD.

46. The process defined by claim 44 wherein the silicon is deposited using PECVD.

47. The process defined by claim 44 wherein the silicon is deposited using PVD.

48. The process defined by claim 44 wherein the silicon is deposited using UHVCVD.

49. A memory array comprising:

a plurality of conductors on levels 1, 2, 3, 4 . . . where the levels are parallel and spaced-apart, the conductors in the odd numbered levels 1,3 . . . running in a first direction, the levels in the even numbered levels 2,4 . . . running in a second direction, generally perpendicular to a first direction, and

a plurality of memory cells each having an input terminal directly connected to a diode terminal with a state change element directly connected between the diode and the output terminal;

wherein the output terminal of the cells are connected to the conductors in the odd numbered levels 1, 3 . . . and the input terminal of the cells are connected to the conductors in the even numbered levels 2, 4 . . . .

50. The array defined by claim 49 wherein the cells have a generally rectangular cross-section.

51. The array defined by claim 49 wherein the cells comprise silicon and silicon dioxide.

52. The array defined by claim 49 wherein the conductors of levels 1, 3 . . . are in vertical alignment with one another.

53. The array defined by claim 49 wherein the conductors in one of the sets of levels 1, 3 . . . and levels 2, 4 . . . are staggered in the vertical direction.

54. The array defined by claim 49 wherein the conductors comprise polysilicon.

55. The array defined by claim 49 wherein the array is fabricated on a silicon substrate.

56. A memory comprising:

a memory array having;

a first plurality of spaced-apart, parallel, substantially coplanar conductors;

a second plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors, said first and second conductors being generally orthogonal to one another;

a plurality of first memory cells, each cell disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors;

a third plurality of spaced-apart, parallel, substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors, the third conductors running in the same direction as the first conductors;

a plurality of second memory cells, each cell disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors, and

a semiconductor substrate on which the array is formed, the substrate containing circuitry for communicating with the first and second memory cells, the circuitry being coupled to the first, second and third plurality of conductors.

57. The memory defined by claim 56 wherein the substrate is silicon.

58. The memory defined by claim 57 wherein the memory cells each comprise a steering element and a state change element.