Semiconductor memory device with decreased current consumption

• US 6,185,137 B1
• Filed: 12/09/1999
• Issued: 02/06/2001
• Est. Priority Date: 03/19/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Sato, Hajime, Kawamoto, Satoru
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/457,370
• Time in Patent Office: 425 Days
• Field of Search: 365/200, 365/201, 365/226, 365/227, 365/203, 365/222, 365/230.03
• US Class Current: 365/200
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device, such as a DRAM, includes multiple cell blocks, each having bit lines and word lines. Block control circuits are connected to respective ones of the cell blocks. The block control circuits supply a precharge signals to their associated cell blocks. A block control circuit which is connected to a defective cell block generates a precharge signal having a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block. The block control circuit sets the precharge signal to the precharge level when the defective cell block is activated and to the reset level when it is deactivated.

Claims

1. A semiconductor memory device comprising:

a plurality of cell blocks each having bit lines and word lines; and

a plurality of block control circuits connected to the plurality of cell blocks, respectively, for supplying a precharge signal to the bit lines of an associated cell block, wherein the block control circuit corresponding to a defective cell block generates the precharge signal having one of a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block.

2. The device according to claim 1, wherein each of the block control circuits sets the precharge signal to its precharge level when the defective cell block is activated and sets the precharge signal to the reset level when the defective cell block is deactivated.

3. The device according to claim 2 further comprising a refresh address counter for outputting a refresh address signal, wherein each of the block control circuits receives the refresh address signal output from the refresh address counter and changes the precharge signal from the reset level to the precharge level before the defective cell block is activated.

4. The device according to claim 3, wherein when the refresh address signal for activating a last word line of the cell block that has been activated before the defective cell block is output from the refresh address counter, each of the block control circuits sets the precharge signal to its precharge level.

5. The device according to claim 3, wherein each of the block control circuits includes:

an address decision circuit connected to the refresh address counter for producing an address decision signal in accordance with the refresh address signal; and

a precharge control circuit connected to the address decision circuit for controlling the level of the precharge signal in accordance with the address decision signal.

6. The device according to claim 5, wherein each of the block control circuits further includes a block selection circuit connected to the precharge control circuit for storing block selection information relating to the defective cell block and for generating a control signal according to the block selection information,

wherein the precharge control circuit controls the level of the precharge signal in accordance with the control signal and the address decision signal.

7. The device according to claim 6, wherein the block selection circuit establishes the level of the control signal according to the block selection information when the operation of the block selection circuit is initiated.

8. The device according to claim 5 further comprising a redundancy decision circuit for generating a redundancy decision signal used to replace a word line located at a defective address in one of the cell blocks by a redundant word line in accordance with the address signal,

wherein the precharge control circuit controls the level of the precharge signal in accordance with the redundancy decision signal.

9. The device according to claim 1, wherein each of the block control circuits receives a test signal used in a probing test to detect defective cell blocks.

10. The device according to claim 1, wherein each of the block control circuits maintains the level of the precharge signal supplied to the cell blocks other than the defective cell block at the precharge level.

11. The device according to claim 1, wherein the defective cell block is previously determined on the basis of at least one of a number of defective addresses within each cell block and the value of a defect current.

12. The device according to claim 11, wherein the defective address refers to an address where a cross-line defect representing an electrical short circuit across a bit line and a word line in one cell block occurs and the defect current refers to a current flow through the cross-line defect.