Magnetic random access memory (MRAM) device including differential sense amplifiers

• US 6,185,143 B1
• Filed: 02/04/2000
• Issued: 02/06/2001
• Est. Priority Date: 02/04/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Eldredge, Kenneth I, Perner, Frederick A, Tran, Lung T
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/498,587
• Time in Patent Office: 368 Days
• Field of Search: 365/157, 365/158, 365/130, 365/145, 365/171, 365/173, 365/205, 365/207, 365/209, 365/210, 365/202
• US Class Current: 365/171
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence

Abstract

Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a differential amplifier, a first current mode preamplifier coupled to a sense node of the differential amplifier, and a second current mode preamplifier coupled to a reference node of the differential amplifier. During a read operation, the first preamplifier applies a regulated voltage to the selected memory cell, and the second preamplifier applies a regulated voltage to a reference cell. A sense current flows through the selected memory cell and to the sense node of the differential amplifier, while a reference current flows through the reference cell and to the reference node of the differential amplifier. Resulting is a differential voltage across sense and reference nodes. The differential voltage indicates whether a logic value of ‘0’ or ‘1’ is stored in the selected memory cell.

Claims

1. Apparatus for sensing a resistance state of a selected memory cell in a magnetic random access memory (MRAM) device, the apparatus comprising:

a differential amplifier having sense and reference nodes;

a first current mode preamplifier coupled between the selected memory cell and the sense node of the differential amplifier;

a reference cell; and

a second current mode preamplifier coupled between the reference cell and the reference node of the differential amplifier.

2. The apparatus of claim 1, wherein the first and second preamplifiers are direct-injection charge amplifiers.

3. The apparatus of claim 1, wherein the first and second preamplifiers are current-mirror amplifiers.

4. The apparatus of claim 1, further comprising a circuit for generating an Equalization signal, the Equalization signal being asserted to cause the sense and reference nodes of the differential amplifier to be equalized, the asserted Equalization signal also causing the differential amplifier to supply a sense current to the selected memory cell and a reference current to the reference cell, a voltage differential developing across the sense and reference nodes after the Equalization signal has been de-asserted, the differential voltage representing the resistance state of the selected memory cell.

5. The apparatus of claim 4, wherein the circuit also generates a Set signal, the Set signal being asserted after the Equalization signal has been de-asserted, the asserted Set signal causing the differential amplifier to amplify the differential voltage.

6. The apparatus of claim 5, further comprising a first switch coupling the first preamplifier to the sense node;

and a second switch coupling the second preamplifier to the reference node;

wherein the circuit also generates an Unload signal, the Unload signal being asserted after the Equalization signal is de-asserted but before the Set signal is asserted, the asserted Unload signal causing the first and second switches to disconnect the differential amplifier from the selected memory cell and the reference cell.

7. The apparatus of claim 6, wherein the first and second preamplifiers are first and second direct injection charge amplifiers, wherein the first switch also functions as a current source transistor for the first direct injection charge amplifier;

and wherein the second switch also functions as a current source transistor for the second direct injection charge amplifier.

8. The apparatus of claim 1, wherein the differential amplifier includes a pair of cross-coupled inverters.

9. A magnetic random access memory (MRAM) device comprising:

an array including a plurality of columns of memory cells and at least one column of reference cells;

a plurality of bit lines, each column of memory cells being crossed by a bit line, each column of reference cells being crossed by a reference bit line; and

a read circuit for sensing resistance states of selected memory cells in the array, the read circuit including;

a plurality of steering circuits, each steering circuit having inputs coupled to multiple bit lines crossing the memory cell columns;

a plurality of differential amplifiers, each differential amplifier corresponding to a steering circuit, each differential amplifier having a sense node and a reference node;

a plurality of first current mode preamplifiers, each first current mode preamplifier being coupled between an output of a corresponding steering circuit and the sense node of a corresponding differential amplifier; and

a plurality of second current mode preamplifiers, each second current mode preamplifier being coupled between the reference node of the corresponding differential amplifier and the reference bit line crossing a reference cell column.

10. The device of claim 9, wherein the device includes a single column of reference cells;

and wherein the reference bit line crossing the single column of reference cells is connected to the reference node of each differential amplifier.

11. The device of claim 9, wherein the device includes a plurality of reference cell columns, each reference cell column corresponding to a differential amplifier;

and wherein the reference bit line crossing a reference cell column is connected to the reference node of the corresponding differential amplifier.

12. The device of claim 9, wherein the device includes a plurality of reference cell columns, each reference cell column corresponding to a memory cell column;

wherein the bit line crossing the memory cell column and the reference bit line crossing the corresponding reference cell column are connected to the same steering circuit.

13. The device of claim 9, wherein the first and second preamplifiers are direct-injection charge amplifiers.

14. The device of claim 9, wherein the first and second preamplifiers are current-mirror amplifiers.

15. The device of claim 9, further comprising at least one clock generator for generating an Equalization signal, the Equalization signal being asserted to cause the sense and reference nodes of the differential amplifier to be equalized, the asserted Equalization signal also causing at least one differential amplifier to pull its node voltages toward a source voltage, a voltage differential developing across the sense and reference nodes of at least one differential amplifier after the Equalization signal has been deasserted.

16. The device of claim 15, wherein each clock generator also generates a Set signal, the Set signal being asserted after the Equalization signal has been de-asserted.

17. The device of claim 16, further comprising a plurality of first and second switches, each first switch coupling a corresponding first preamplifier to the sense node of a corresponding differential amplifier, each second switch coupling a corresponding second preamplifier to the reference node of the corresponding differential amplifier;

wherein each clock generator also generates an Unload signal, the Unload signal being asserted after the Equalization signal is de-asserted but before the Set signal is asserted, the asserted Unload signal causing the first and second switches to disconnect their corresponding differential amplifier from their corresponding first and second preamplifiers.

18. A method of using a differential amplifier and a reference cell to sense a resistance state of a memory cell in a magnetic random access memory (MRAM) device, the differential amplifier having sense and reference nodes, the method comprising the steps of:

asserting an Equalization signal, the asserted equalization signal causing sense and reference node voltages to be equalized, the asserted Equalization signal also causing currents to flow through the memory and reference cells and to the sense and reference nodes;

regulating voltages across the memory and reference cells while the currents are flowing through the cells;

de-asserting the Equalization signal, whereby a differential voltage across the differential amplifier begins to form;

holding the differential voltage after a period of time, the voltage being held representing the resistance state of the selected memory cell.

19. The method of claim 18, wherein the differential voltage is held by disconnecting the differential amplifier from the memory and reference cells.

20. The method of claim 18, further comprising the step of pulling each node of the differential amplifier to a full logic swing after the differential voltage has been held for the period of time.