Magnetic random access memory (MRAM) device including differential sense amplifiers
First Claim
1. Apparatus for sensing a resistance state of a selected memory cell in a magnetic random access memory (MRAM) device, the apparatus comprising:
- a differential amplifier having sense and reference nodes;
a first current mode preamplifier coupled between the selected memory cell and the sense node of the differential amplifier;
a reference cell; and
a second current mode preamplifier coupled between the reference cell and the reference node of the differential amplifier.
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Accused Products
Abstract
Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a differential amplifier, a first current mode preamplifier coupled to a sense node of the differential amplifier, and a second current mode preamplifier coupled to a reference node of the differential amplifier. During a read operation, the first preamplifier applies a regulated voltage to the selected memory cell, and the second preamplifier applies a regulated voltage to a reference cell. A sense current flows through the selected memory cell and to the sense node of the differential amplifier, while a reference current flows through the reference cell and to the reference node of the differential amplifier. Resulting is a differential voltage across sense and reference nodes. The differential voltage indicates whether a logic value of ‘0’ or ‘1’ is stored in the selected memory cell.
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Citations
20 Claims
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1. Apparatus for sensing a resistance state of a selected memory cell in a magnetic random access memory (MRAM) device, the apparatus comprising:
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a differential amplifier having sense and reference nodes;
a first current mode preamplifier coupled between the selected memory cell and the sense node of the differential amplifier;
a reference cell; and
a second current mode preamplifier coupled between the reference cell and the reference node of the differential amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A magnetic random access memory (MRAM) device comprising:
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an array including a plurality of columns of memory cells and at least one column of reference cells;
a plurality of bit lines, each column of memory cells being crossed by a bit line, each column of reference cells being crossed by a reference bit line; and
a read circuit for sensing resistance states of selected memory cells in the array, the read circuit including;
a plurality of steering circuits, each steering circuit having inputs coupled to multiple bit lines crossing the memory cell columns;
a plurality of differential amplifiers, each differential amplifier corresponding to a steering circuit, each differential amplifier having a sense node and a reference node;
a plurality of first current mode preamplifiers, each first current mode preamplifier being coupled between an output of a corresponding steering circuit and the sense node of a corresponding differential amplifier; and
a plurality of second current mode preamplifiers, each second current mode preamplifier being coupled between the reference node of the corresponding differential amplifier and the reference bit line crossing a reference cell column. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of using a differential amplifier and a reference cell to sense a resistance state of a memory cell in a magnetic random access memory (MRAM) device, the differential amplifier having sense and reference nodes, the method comprising the steps of:
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asserting an Equalization signal, the asserted equalization signal causing sense and reference node voltages to be equalized, the asserted Equalization signal also causing currents to flow through the memory and reference cells and to the sense and reference nodes;
regulating voltages across the memory and reference cells while the currents are flowing through the cells;
de-asserting the Equalization signal, whereby a differential voltage across the differential amplifier begins to form;
holding the differential voltage after a period of time, the voltage being held representing the resistance state of the selected memory cell. - View Dependent Claims (19, 20)
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Specification